A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC

Huan Jui Hu, Yi Shen Cheng, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm2

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728103976
DOIs
Publication statusPublished - 2019 Jan 1
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: 2019 May 262019 May 29

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2019-May
ISSN (Print)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
CountryJapan
CitySapporo
Period19-05-2619-05-29

Fingerprint

Digital to analog conversion
Calibration
Clocks
Switches
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Hu, H. J., Cheng, Y. S., & Chang, S-J. (2019). A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings [8702455] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702455
Hu, Huan Jui ; Cheng, Yi Shen ; Chang, Soon-Jyh. / A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC. 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - IEEE International Symposium on Circuits and Systems).
@inproceedings{e5ac5094ed2d446aa95794fa4845d818,
title = "A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC",
abstract = "This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm2",
author = "Hu, {Huan Jui} and Cheng, {Yi Shen} and Soon-Jyh Chang",
year = "2019",
month = "1",
day = "1",
doi = "10.1109/ISCAS.2019.8702455",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings",
address = "United States",

}

Hu, HJ, Cheng, YS & Chang, S-J 2019, A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702455, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 19-05-26. https://doi.org/10.1109/ISCAS.2019.8702455

A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC. / Hu, Huan Jui; Cheng, Yi Shen; Chang, Soon-Jyh.

2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702455 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC

AU - Hu, Huan Jui

AU - Cheng, Yi Shen

AU - Chang, Soon-Jyh

PY - 2019/1/1

Y1 - 2019/1/1

N2 - This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm2

AB - This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm2

UR - http://www.scopus.com/inward/record.url?scp=85066781432&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85066781432&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2019.8702455

DO - 10.1109/ISCAS.2019.8702455

M3 - Conference contribution

AN - SCOPUS:85066781432

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Hu HJ, Cheng YS, Chang S-J. A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702455. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2019.8702455