@inproceedings{e5ac5094ed2d446aa95794fa4845d818,
title = "A 10-bit 1-GS/s 2x-interleaved timing-skew calibration free SAR ADC",
abstract = "This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm2",
author = "Hu, {Huan Jui} and Cheng, {Yi Shen} and Chang, {Soon Jyh}",
note = "Funding Information: ACKNOWLEDGMENT This work was supported by Ministry of Science and Technology of Taiwan under grant MOST-107-2218-E-006-028. Publisher Copyright: {\textcopyright} 2019 IEEE; 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 ; Conference date: 26-05-2019 Through 29-05-2019",
year = "2019",
doi = "10.1109/ISCAS.2019.8702455",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings",
address = "United States",
}