A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance

Guan Ying Huang, Chun Cheng Liu, Ying Zu Lin, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-μm CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.

Original languageEnglish
Title of host publicationProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages157-160
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan
Duration: 2009 Nov 162009 Nov 18

Publication series

NameProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Other

Other2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Country/TerritoryTaiwan
CityTaipei
Period09-11-1609-11-18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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