TY - JOUR
T1 - A 10-Bit 20 Channel LCD Column Driver Using Compact DAC
AU - Agarwal, Neeraj
AU - Agarwal, Neeru
AU - Lu, Chih Wen
N1 - Publisher Copyright:
© 2023 World Scientific Publishing Company.
PY - 2023/9/15
Y1 - 2023/9/15
N2 - A 20-channel liquid crystal display (LCD) driver architecture is implemented with 0.18μm CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using 0.18μm CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140 dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25-1.7 V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and -0.12 LSB, respectively. The one channel area is 951.69μm × 17.8μm and the settling time is 5.65μs for the 20kω and 20 pF driving load.
AB - A 20-channel liquid crystal display (LCD) driver architecture is implemented with 0.18μm CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using 0.18μm CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140 dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25-1.7 V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and -0.12 LSB, respectively. The one channel area is 951.69μm × 17.8μm and the settling time is 5.65μs for the 20kω and 20 pF driving load.
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U2 - 10.1142/S0218126623502225
DO - 10.1142/S0218126623502225
M3 - Article
AN - SCOPUS:85150693325
SN - 0218-1266
VL - 32
JO - Journal of Circuits, Systems and Computers
JF - Journal of Circuits, Systems and Computers
IS - 13
M1 - 2350222
ER -