A 10-bit 350-MSample/s Nyquist CMOS D/A converter

Jeng Dau Chang, Hsin Hung Ou, Bin-Da Liu

Research output: Contribution to conferencePaper

Abstract

A 10-bit 350-MSample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed in this paper. Segmented current steering architecture that comprises 6MSB's unary cells and 4LSB's binary-weighted cells is applied in this design. Cascoded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5V supply is 36mW for a near-Nyquist fundamental signal at a 350-MHz update rate.

Original languageEnglish
Pages621-624
Number of pages4
Publication statusPublished - 2004 Dec 1
Event2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan
Duration: 2004 Dec 62004 Dec 9

Other

Other2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
CountryTaiwan
CityTainan
Period04-12-0604-12-09

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Chang, J. D., Ou, H. H., & Liu, B-D. (2004). A 10-bit 350-MSample/s Nyquist CMOS D/A converter. 621-624. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan.