A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers

Shao Hua Wan, Che Hsun Kuo, Soon-Jyh Chang, Guan Ying Huang, Chun Po Huang, Goh Jih Ren, Kai Tzeng Chiou, Cheng Hsun Ho

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

A high speed successive approximation (SAR) ADC requires reference voltage buffers with high driving capability. Moreover, the power consumption of the reference buffers is usually several times larger than that of the SAR ADC itself. Three techniques are adopted to mitigate the requirement on driving capability of reference voltage buffers for SAR ADCs. A 10b 50MS/s ADC based on the proposed techniques is presented. The prototype ADC was fabricated in 40nm LP 1P7M CMOS technology. It consumes 0.47 mW at 50 MS/s from 1.1V supply voltage and achieves ENOB of 9.18-bit and figure of merit (FoM) of 16 fJ/conversion-step. The active area is 0.0114 mm2.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages293-296
Number of pages4
DOIs
Publication statusPublished - 2013
Event2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore
Duration: 2013 Nov 112013 Nov 13

Other

Other2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
CountrySingapore
CitySingapore
Period13-11-1113-11-13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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