A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique

Jin Fu Lin, Soon Jyh Chang, Chun Cheng Liu, Chih Hao Huang

Research output: Contribution to journalArticle

24 Citations (Scopus)

Abstract

In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.

Original languageEnglish
Article number5431013
Pages (from-to)163-167
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number3
DOIs
Publication statusPublished - 2010 Mar 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique'. Together they form a unique fingerprint.

  • Cite this