A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique

Jin Fu Lin; Soon Jyh Chang; Chun Cheng Liu; Chih Hao Huang

doi:10.1109/TCSII.2010.2040307

A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique

Jin Fu Lin, Soon Jyh Chang, Chun Cheng Liu, Chih Hao Huang

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

26 Citations (Scopus)

Abstract

In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm².

Original language	English
Article number	5431013
Pages (from-to)	163-167
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2010.2040307
Publication status	Published - 2010 Mar

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2010.2040307

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title = "A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique",

abstract = "In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.",

author = "Lin, {Jin Fu} and Chang, {Soon Jyh} and Liu, {Chun Cheng} and Huang, {Chih Hao}",

note = "Funding Information: Manuscript received September 19, 2009; revised November 14, 2009. Current version published March 17, 2010. This work was supported in part by the National Science Council and in part by Himax Technologies Inc., Taiwan, under Grant NSC-98-2221-E-006-156-MY3 and Grant NSC 98-2218-E-006-003. This paper was recommended by Associate Editor Y. Chiu.",

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doi = "10.1109/TCSII.2010.2040307",

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AU - Huang, Chih Hao

N1 - Funding Information: Manuscript received September 19, 2009; revised November 14, 2009. Current version published March 17, 2010. This work was supported in part by the National Science Council and in part by Himax Technologies Inc., Taiwan, under Grant NSC-98-2221-E-006-156-MY3 and Grant NSC 98-2218-E-006-003. This paper was recommended by Associate Editor Y. Chiu.

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N2 - In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.

AB - In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.

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A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique

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