Abstract
In this brief, a split-capacitor correlated double sampling (SC-CDS) technique is proposed to improve the performance of CDS. Using the proposed technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined analog-to-digital converter (ADC). A power-efficient class-AB pseudodifferential op-amp and its corresponding integrator-based common-mode stabilization (IB-CMS) method are developed to further reduce the power consumption of the ADC. The proposed pipelined ADC fabricated in a pure digital 0.18-μ 1P5M CMOS process consumes 18 mW at 60 MS/s from a 1.8-V power supply. The active die area is 0.84 mm2.
| Original language | English |
|---|---|
| Article number | 5431013 |
| Pages (from-to) | 163-167 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 57 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2010 Mar 1 |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Lin, J. F., Chang, S. J., Liu, C. C., & Huang, C. H. (2010). A 10-bit 60-MS/s low-power pipelined ADC with split-capacitor CDS technique. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(3), 163-167. [5431013]. https://doi.org/10.1109/TCSII.2010.2040307