A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits

Keng Hong Chu, Tse An Chen, Chia Ling Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.

Original languageEnglish
Title of host publication2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509024391
DOIs
Publication statusPublished - 2016 Aug 12
Event5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
Duration: 2016 May 42016 May 6

Publication series

Name2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other5th International Symposium on Next-Generation Electronics, ISNE 2016
CountryTaiwan
CityHsinchu
Period16-05-0416-05-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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