Abstract
A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.
| Original language | English |
|---|---|
| Title of host publication | 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781509024391 |
| DOIs | |
| Publication status | Published - 2016 Aug 12 |
| Event | 5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan Duration: 2016 May 4 → 2016 May 6 |
Publication series
| Name | 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 |
|---|
Other
| Other | 5th International Symposium on Next-Generation Electronics, ISNE 2016 |
|---|---|
| Country | Taiwan |
| City | Hsinchu |
| Period | 16-05-04 → 16-05-06 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
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A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits. / Chu, Keng Hong; Chen, Tse An; Wei, Chia-Ling.
2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7543359 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits
AU - Chu, Keng Hong
AU - Chen, Tse An
AU - Wei, Chia-Ling
PY - 2016/8/12
Y1 - 2016/8/12
N2 - A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.
AB - A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.
UR - http://www.scopus.com/inward/record.url?scp=84985916598&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84985916598&partnerID=8YFLogxK
U2 - 10.1109/ISNE.2016.7543359
DO - 10.1109/ISNE.2016.7543359
M3 - Conference contribution
T3 - 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
BT - 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PB - Institute of Electrical and Electronics Engineers Inc.
ER -