A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits

Keng Hong Chu; Tse An Chen; Chia Ling Wei

doi:10.1109/ISNE.2016.7543359

A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits

Keng Hong Chu, Tse An Chen, Chia Ling Wei

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm².

Original language	English
Title of host publication	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509024391
DOIs	https://doi.org/10.1109/ISNE.2016.7543359
Publication status	Published - 2016 Aug 12
Event	5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan Duration: 2016 May 4 → 2016 May 6

Publication series

Name	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other	5th International Symposium on Next-Generation Electronics, ISNE 2016
Country/Territory	Taiwan
City	Hsinchu
Period	16-05-04 → 16-05-06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISNE.2016.7543359

Cite this

Chu, K. H., Chen, T. A., & Wei, C. L. (2016). A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits. In 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 Article 7543359 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISNE.2016.7543359

Chu, Keng Hong ; Chen, Tse An ; Wei, Chia Ling. / A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits. 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

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title = "A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits",

abstract = "A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.",

author = "Chu, {Keng Hong} and Chen, {Tse An} and Wei, {Chia Ling}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 5th International Symposium on Next-Generation Electronics, ISNE 2016 ; Conference date: 04-05-2016 Through 06-05-2016",

year = "2016",

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doi = "10.1109/ISNE.2016.7543359",

language = "English",

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Chu, KH, Chen, TA & Wei, CL 2016, A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits. in 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016., 7543359, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016, Institute of Electrical and Electronics Engineers Inc., 5th International Symposium on Next-Generation Electronics, ISNE 2016, Hsinchu, Taiwan, 16-05-04. https://doi.org/10.1109/ISNE.2016.7543359

A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits. / Chu, Keng Hong; Chen, Tse An; Wei, Chia Ling.
2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7543359 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.

AB - A 10-bit segmented digital-to-time converter (DTC) with offset calibration is proposed. The segmented architecture (2-bit binary code + 8-bit thermometer code) is adopted in the proposed DTC to reduce the impact of process variation on linearity. Moreover, the relative time generation is used for getting high resolution, and the offset calibration circuit is also implemented to calibrate the offset error inherent in the relative time generation. The proposed DTC was fabricated using the TSMC 0.18μm 1P6M mixed-signal process. The resolution is designed to be in the order of 10ps, and the total output timing range is in the order of 10 ns. The core area is 0.7mm2.

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Chu KH, Chen TA, Wei CL. A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits. In 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7543359. (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). doi: 10.1109/ISNE.2016.7543359

A 10-bit segmented digital-to-time converter with 10-ps-level resolution and offset calibration circuits

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