A 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC

Chih Wen Lu; Yen Chung Huang

A 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC

Chih Wen Lu
, Yen Chung Huang

Program on Integrated Circuit Design

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This study proposes a 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC. The 10-bit DACs are divided into positive 9-bit and negative 9-bit components to save the silicon die area. Each output channel combines a 6-bit two-voltage selector and a 3-bit RDAC-embedded op-amp in a cascaded manner. The 10-bit column driver prototype was realized in 0.18-pm CMOS technology with the worst DNL/INL being 0.29/0.72 LSB. The silicon area is only 11 × 373 μm² for each output channel.

Original language	English
Title of host publication	24th International Display Workshops, IDW 2017
Publisher	International Display Workshops
Pages	1477-1480
Number of pages	4
ISBN (Electronic)	9781510858992
Publication status	Published - 2017
Event	24th International Display Workshops, IDW 2017 - Sendai, Japan Duration: 2017 Dec 6 → 2017 Dec 8

Publication series

Name	Proceedings of the International Display Workshops
Volume	2
ISSN (Print)	1883-2490

Other

Other	24th International Display Workshops, IDW 2017
Country/Territory	Japan
City	Sendai
Period	17-12-06 → 17-12-08

All Science Journal Classification (ASJC) codes

Computer Vision and Pattern Recognition
Human-Computer Interaction
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Radiology Nuclear Medicine and imaging

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Cite this

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title = "A 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC",

abstract = "This study proposes a 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC. The 10-bit DACs are divided into positive 9-bit and negative 9-bit components to save the silicon die area. Each output channel combines a 6-bit two-voltage selector and a 3-bit RDAC-embedded op-amp in a cascaded manner. The 10-bit column driver prototype was realized in 0.18-pm CMOS technology with the worst DNL/INL being 0.29/0.72 LSB. The silicon area is only 11 × 373 μm2 for each output channel.",

author = "Lu, \{Chih Wen\} and Huang, \{Yen Chung\}",

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year = "2017",

language = "English",

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N2 - This study proposes a 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC. The 10-bit DACs are divided into positive 9-bit and negative 9-bit components to save the silicon die area. Each output channel combines a 6-bit two-voltage selector and a 3-bit RDAC-embedded op-amp in a cascaded manner. The 10-bit column driver prototype was realized in 0.18-pm CMOS technology with the worst DNL/INL being 0.29/0.72 LSB. The silicon area is only 11 × 373 μm2 for each output channel.

AB - This study proposes a 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC. The 10-bit DACs are divided into positive 9-bit and negative 9-bit components to save the silicon die area. Each output channel combines a 6-bit two-voltage selector and a 3-bit RDAC-embedded op-amp in a cascaded manner. The 10-bit column driver prototype was realized in 0.18-pm CMOS technology with the worst DNL/INL being 0.29/0.72 LSB. The silicon area is only 11 × 373 μm2 for each output channel.

UR - https://www.scopus.com/pages/publications/85056172265

UR - https://www.scopus.com/pages/publications/85056172265#tab=citedBy

M3 - Conference contribution

AN - SCOPUS:85056172265

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BT - 24th International Display Workshops, IDW 2017

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T2 - 24th International Display Workshops, IDW 2017

Y2 - 6 December 2017 through 8 December 2017

ER -

A 10-bit two-stage DAC with an RDAC-embedded op-amp for TFT-LCD Column Driver IC

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

UN SDGs

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