A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

Yen Long Lee, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 6 Gb/s low-power half-rate equalizer. Compared with the current steering summation circuits, the proposed charge-average switched-capacitor equalizer achieves good energy and area efficiency, and thus is suitable for multi-lane applications. The proposed architecture are majorly constructed by switched-capacitor and digital circuitries, it is hence suitable for advanced manufacturing process. The proof-of-concept prototype was fabricated in TSMC 0.18 um CMOS technology. It occupies 0.0034 mm2 area and the figure of merit is 10 fJ/bit/dB while operating at a bit-error-rate < 10-12 for 6 Gb/s data passed over a 100 cm FR4 PCB channel with 23.2 dB channel loss at 3 GHz.

Original languageEnglish
Title of host publication2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509024391
DOIs
Publication statusPublished - 2016 Aug 12
Event5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
Duration: 2016 May 42016 May 6

Publication series

Name2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Other

Other5th International Symposium on Next-Generation Electronics, ISNE 2016
CountryTaiwan
CityHsinchu
Period16-05-0416-05-06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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