A 100 W 5.1-channel digital class-D audio amplifier with single-chip design

Jia Ming Liu, Shih Hsiung Chien, Tai-Haur Kuo

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2.

Original languageEnglish
Article number6177693
Pages (from-to)1344-1354
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume47
Issue number6
DOIs
Publication statusPublished - 2012 Apr 5

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Electric potential
Pulse width modulation
Modulators
Digital circuits
Resonators
Networks (circuits)
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{9c39c18f3a834ceb8399a81dd1f0a680,
title = "A 100 W 5.1-channel digital class-D audio amplifier with single-chip design",
abstract = "A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7{\%}, and a power efficiency of 88{\%} with a total chip area of 48.9 mm 2.",
author = "Liu, {Jia Ming} and Chien, {Shih Hsiung} and Tai-Haur Kuo",
year = "2012",
month = "4",
day = "5",
doi = "10.1109/JSSC.2012.2188465",
language = "English",
volume = "47",
pages = "1344--1354",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

A 100 W 5.1-channel digital class-D audio amplifier with single-chip design. / Liu, Jia Ming; Chien, Shih Hsiung; Kuo, Tai-Haur.

In: IEEE Journal of Solid-State Circuits, Vol. 47, No. 6, 6177693, 05.04.2012, p. 1344-1354.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 100 W 5.1-channel digital class-D audio amplifier with single-chip design

AU - Liu, Jia Ming

AU - Chien, Shih Hsiung

AU - Kuo, Tai-Haur

PY - 2012/4/5

Y1 - 2012/4/5

N2 - A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2.

AB - A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm 2.

UR - http://www.scopus.com/inward/record.url?scp=84861719095&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84861719095&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2012.2188465

DO - 10.1109/JSSC.2012.2188465

M3 - Article

VL - 47

SP - 1344

EP - 1354

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 6

M1 - 6177693

ER -