TY - GEN
T1 - A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
AU - Liu, Chun Cheng
AU - Chang, Soon Jyh
AU - Huang, Guan Ying
AU - Lin, Ying Zu
AU - Huang, Chung Ming
AU - Huang, Chih Hao
AU - Bu, Linkai
AU - Tsai, Chih Chung
PY - 2010/5/18
Y1 - 2010/5/18
N2 - In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]-[4]. When the sampling rate increases, the SAR ADCs suffer from settling issues. In a typical 10b 100MS/s ADC, when the sampling settling time, comparator active time and SAR logic delay are subtracted from each period, the DAC settling time has to be less than 0.4ns in each bit cycle. Such a short time interval is not sufficient for the capacitive DAC to stabilize because the increasing interconnect line impedance in advanced processes slows down the charge transfer, especially in the longest routing path of the DAC capacitor network. Furthermore, the reference voltage sinks noise and line coupling also affects the settling. A non-binary SAR can tolerate DAC settling error at the cost of increased design complexity and hardware overhead [1]. This paper reports a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. The ADC achieves 100MS/s while consuming only 1.13mW.
AB - In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]-[4]. When the sampling rate increases, the SAR ADCs suffer from settling issues. In a typical 10b 100MS/s ADC, when the sampling settling time, comparator active time and SAR logic delay are subtracted from each period, the DAC settling time has to be less than 0.4ns in each bit cycle. Such a short time interval is not sufficient for the capacitive DAC to stabilize because the increasing interconnect line impedance in advanced processes slows down the charge transfer, especially in the longest routing path of the DAC capacitor network. Furthermore, the reference voltage sinks noise and line coupling also affects the settling. A non-binary SAR can tolerate DAC settling error at the cost of increased design complexity and hardware overhead [1]. This paper reports a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. The ADC achieves 100MS/s while consuming only 1.13mW.
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U2 - 10.1109/ISSCC.2010.5433970
DO - 10.1109/ISSCC.2010.5433970
M3 - Conference contribution
AN - SCOPUS:77952141253
SN - 9781424460342
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 386
EP - 387
BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
T2 - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
Y2 - 7 February 2010 through 11 February 2010
ER -