A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun Cheng Liu, Soon Jyh Chang, Guan Ying Huang, Ying Zu Lin, Chung Ming Huang, Chih Hao Huang, Linkai Bu, Chih Chung Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

224 Citations (Scopus)

Abstract

In recent years, due to the improvements in CMOS technologies, medium resolution (8 to 10b) SAR ADCs have been able to achieve sampling rates of several tens of MS/s with excellent power efficiency and small area [1]-[4]. When the sampling rate increases, the SAR ADCs suffer from settling issues. In a typical 10b 100MS/s ADC, when the sampling settling time, comparator active time and SAR logic delay are subtracted from each period, the DAC settling time has to be less than 0.4ns in each bit cycle. Such a short time interval is not sufficient for the capacitive DAC to stabilize because the increasing interconnect line impedance in advanced processes slows down the charge transfer, especially in the longest routing path of the DAC capacitor network. Furthermore, the reference voltage sinks noise and line coupling also affects the settling. A non-binary SAR can tolerate DAC settling error at the cost of increased design complexity and hardware overhead [1]. This paper reports a 10b SAR ADC that uses binary-scaled DAC networks for settling error compensation. The ADC achieves 100MS/s while consuming only 1.13mW.

Original languageEnglish
Title of host publication2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages386-387
Number of pages2
DOIs
Publication statusPublished - 2010 May 18
Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
Duration: 2010 Feb 72010 Feb 11

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume53
ISSN (Print)0193-6530

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
CountryUnited States
CitySan Francisco, CA
Period10-02-0710-02-11

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Liu, C. C., Chang, S. J., Huang, G. Y., Lin, Y. Z., Huang, C. M., Huang, C. H., Bu, L., & Tsai, C. C. (2010). A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 386-387). [5433970] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5433970