A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Chua Chin Wang, Ralph Gerard B. Sangalang, I. Ting Tseng, Yi Jen Chiu, Yu Cheng Lin, Oliver Lexter July A. Jose

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and power-delay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.

Original languageEnglish
Pages (from-to)75-87
Number of pages13
JournalIET Circuits, Devices and Systems
Issue number2
Publication statusPublished - 2023 Mar

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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