A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process

Wen Chia Luo, Soon Jyh Chang, Chun Po Huang, Hao Sheng Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an 11-bit 35-MS/s wide input range successive approximation register (SAR) analog-to-digital converter (ADC). A built-in magnitude-reduction front-end circuit is integrated with the SAR ADC to deal with high voltage input signal without using power-hungry programmable gain amplifier (PGA). The front-end circuit is implemented by switched-capacitor (SC) circuit without high voltage devices, which is low power, compact and easy to integrate with the SAR ADC. The proof-of-concept prototype was fabricated in TSMC 180-nm CMOS technology. At 1.8V supply and Nyquist input frequency, the ADC achieves an SNDR of 67.89 dB and total power consumption of 3.4 mW (including front-end circuit), resulting in a figure-of-merit (FoM) of 47.96 fJ/conv.-step.

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538642603
DOIs
Publication statusPublished - 2018 Jun 5
Event2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 - Hsinchu, Taiwan
Duration: 2018 Apr 162018 Apr 19

Publication series

Name2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018

Other

Other2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
CountryTaiwan
CityHsinchu
Period18-04-1618-04-19

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality
  • Control and Optimization
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Luo, W. C., Chang, S. J., Huang, C. P., & Wu, H. S. (2018). A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process. In 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 (pp. 1-4). (2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2018.8373252