A 12-b 40-MS/s Calibration-Free SAR ADC

Chung Wei Hsu, Soon Jyh Chang, Chun Po Huang, Li Jen Chang, Ya Ting Shyu, Chih Huei Hou, Hwa An Tseng, Chih Yuan Kung, Huan Jui Hu

Research output: Contribution to journalArticlepeer-review

22 Citations (Scopus)


This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.

Original languageEnglish
Pages (from-to)881-890
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number3
Publication statusPublished - 2018 Mar

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'A 12-b 40-MS/s Calibration-Free SAR ADC'. Together they form a unique fingerprint.

Cite this