A 12-b 40-MS/s Calibration-Free SAR ADC

Chung Wei Hsu, Soon Jyh Chang, Chun Po Huang, Li Jen Chang, Ya Ting Shyu, Chih Huei Hou, Hwa An Tseng, Chih Yuan Kung, Huan Jui Hu

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.

Original languageEnglish
Pages (from-to)881-890
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number3
DOIs
Publication statusPublished - 2018 Mar

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Digital to analog conversion
Calibration
Capacitors
Sampling
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Hsu, C. W., Chang, S. J., Huang, C. P., Chang, L. J., Shyu, Y. T., Hou, C. H., ... Hu, H. J. (2018). A 12-b 40-MS/s Calibration-Free SAR ADC. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(3), 881-890. https://doi.org/10.1109/TCSI.2017.2771364
Hsu, Chung Wei ; Chang, Soon Jyh ; Huang, Chun Po ; Chang, Li Jen ; Shyu, Ya Ting ; Hou, Chih Huei ; Tseng, Hwa An ; Kung, Chih Yuan ; Hu, Huan Jui. / A 12-b 40-MS/s Calibration-Free SAR ADC. In: IEEE Transactions on Circuits and Systems I: Regular Papers. 2018 ; Vol. 65, No. 3. pp. 881-890.
@article{b91c94277df54cf39fdc43c0d4412682,
title = "A 12-b 40-MS/s Calibration-Free SAR ADC",
abstract = "This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.",
author = "Hsu, {Chung Wei} and Chang, {Soon Jyh} and Huang, {Chun Po} and Chang, {Li Jen} and Shyu, {Ya Ting} and Hou, {Chih Huei} and Tseng, {Hwa An} and Kung, {Chih Yuan} and Hu, {Huan Jui}",
year = "2018",
month = "3",
doi = "10.1109/TCSI.2017.2771364",
language = "English",
volume = "65",
pages = "881--890",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1057-7122",
number = "3",

}

Hsu, CW, Chang, SJ, Huang, CP, Chang, LJ, Shyu, YT, Hou, CH, Tseng, HA, Kung, CY & Hu, HJ 2018, 'A 12-b 40-MS/s Calibration-Free SAR ADC', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 3, pp. 881-890. https://doi.org/10.1109/TCSI.2017.2771364

A 12-b 40-MS/s Calibration-Free SAR ADC. / Hsu, Chung Wei; Chang, Soon Jyh; Huang, Chun Po; Chang, Li Jen; Shyu, Ya Ting; Hou, Chih Huei; Tseng, Hwa An; Kung, Chih Yuan; Hu, Huan Jui.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 3, 03.2018, p. 881-890.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A 12-b 40-MS/s Calibration-Free SAR ADC

AU - Hsu, Chung Wei

AU - Chang, Soon Jyh

AU - Huang, Chun Po

AU - Chang, Li Jen

AU - Shyu, Ya Ting

AU - Hou, Chih Huei

AU - Tseng, Hwa An

AU - Kung, Chih Yuan

AU - Hu, Huan Jui

PY - 2018/3

Y1 - 2018/3

N2 - This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.

AB - This paper presents a new circuit technique named residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying the dynamic element matching, the impacts of capacitor mismatch and noise upon the successive-approximation register ADCs are reduced significantly without calibrations. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise and distortion ratios are 66.84 and 69.78 dB, respectively.

UR - http://www.scopus.com/inward/record.url?scp=85037553635&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85037553635&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2017.2771364

DO - 10.1109/TCSI.2017.2771364

M3 - Article

AN - SCOPUS:85037553635

VL - 65

SP - 881

EP - 890

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1057-7122

IS - 3

ER -