TY - GEN
T1 - A 12-bit 40-MS/s calibration-free SAR ADC
AU - Hsu, Chung Wei
AU - Chang, Li Jen
AU - Huang, Chun Po
AU - Chang, Soon Jyh
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by the grant from Ministry of Science and Technology in Taiwan under Grant MOST 105-2221-E-006-240-MY3. We also thank the fabrication and measurement supports of the Chip Implementation Center (CIC), Taiwan.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.
AB - This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.
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U2 - 10.1109/ISCAS.2017.8050307
DO - 10.1109/ISCAS.2017.8050307
M3 - Conference contribution
AN - SCOPUS:85032688395
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -