A 12-bit 40-MS/s calibration-free SAR ADC

Chung Wei Hsu; Li Jen Chang; Chun Po Huang; Soon Jyh Chang

doi:10.1109/ISCAS.2017.8050307

A 12-bit 40-MS/s calibration-free SAR ADC

Chung Wei Hsu, Li Jen Chang, Chun Po Huang, Soon Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050307
Publication status	Published - 2017 Sep 25
Event	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: 2017 May 28 → 2017 May 31

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country	United States
City	Baltimore
Period	17-05-28 → 17-05-31

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2017.8050307

Fingerprint Dive into the research topics of 'A 12-bit 40-MS/s calibration-free SAR ADC'. Together they form a unique fingerprint.

Cite this

Hsu, C. W., Chang, L. J., Huang, C. P., & Chang, S. J. (2017). A 12-bit 40-MS/s calibration-free SAR ADC. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050307] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050307

@inproceedings{5516d552000a4b8eae6fb28f27c379a0,

title = "A 12-bit 40-MS/s calibration-free SAR ADC",

abstract = "This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.",

author = "Hsu, {Chung Wei} and Chang, {Li Jen} and Huang, {Chun Po} and Chang, {Soon Jyh}",

year = "2017",

month = sep,

day = "25",

doi = "10.1109/ISCAS.2017.8050307",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "IEEE International Symposium on Circuits and Systems",

address = "United States",

note = "50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

}

Hsu, CW, Chang, LJ, Huang, CP & Chang, SJ 2017, A 12-bit 40-MS/s calibration-free SAR ADC. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050307, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 17-05-28. https://doi.org/10.1109/ISCAS.2017.8050307

A 12-bit 40-MS/s calibration-free SAR ADC. / Hsu, Chung Wei; Chang, Li Jen; Huang, Chun Po; Chang, Soon Jyh.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050307 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 12-bit 40-MS/s calibration-free SAR ADC

AU - Hsu, Chung Wei

AU - Chang, Li Jen

AU - Huang, Chun Po

AU - Chang, Soon Jyh

PY - 2017/9/25

Y1 - 2017/9/25

N2 - This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.

AB - This paper presents a new circuit technique named as residue oversampling, which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.

UR - http://www.scopus.com/inward/record.url?scp=85032688395&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85032688395&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2017.8050307

DO - 10.1109/ISCAS.2017.8050307

M3 - Conference contribution

AN - SCOPUS:85032688395

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -

Hsu CW, Chang LJ, Huang CP, Chang SJ. A 12-bit 40-MS/s calibration-free SAR ADC. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050307. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2017.8050307