TY - GEN
T1 - A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM
AU - Sun, Wei Hao
AU - Chien, Shih Hsiung
AU - Kuo, Tai Haur
N1 - Funding Information:
The authors would like to acknowledge the chip fabrication support provided by the Taiwan Semiconductor Research Institute (TSRI), Taiwan.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power (P_OUT) are desired. However, in mobile devices, the P_OUT is limited since Li-ion batteries operate at 3 to 4.2V. To increase P_OUT, prior publications [1]-[3] have developed embedded boost converters to regulate boosted supply voltage V_PVDD to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high P_OUT is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency f_SW, Class) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different P_OUT regions. In the low-P_OUT region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the high-P_OUT region. As such, the maximum P_OUT with THD+N<1 % is decreased, which squanders the boosted V_PVDD. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the low-P_OUT region. As for the medium-P_OUT region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.
AB - Class-D audio amplifiers have gradually become standard components in mobile devices, where better audio quality over a wide volume range and higher output power (P_OUT) are desired. However, in mobile devices, the P_OUT is limited since Li-ion batteries operate at 3 to 4.2V. To increase P_OUT, prior publications [1]-[3] have developed embedded boost converters to regulate boosted supply voltage V_PVDD to 5V or higher for the Class-D power stage at the expense of efficiency degradation. The top of Fig. 31.3.1 shows a typical digital-input open-loop Class-D audio amplifier, where the boost converter is operated only when high P_OUT is required. The input signal is first multiplied by the digital volume level, and then processed by an interpolator and a delta-sigma modulator (DSM) to achieve a high signal-to-quantization-noise ratio (SQNR). Next, the DSM output is converted into a PWM signal with a 384kHz switching frequency f_SW, Class) by the PCM-to-PWM converter to drive the power stage. The bottom of Fig. 31.3.1 illustrates the dominant factors of the THD+N in different P_OUT regions. In the low-P_OUT region, to achieve a high dynamic range (DR), the DSM loop order should be sufficiently high for more aggressive noise-shaping ability so as to suppress the DSM-shaped quantization noise. However, this tends to overload the DSM's quantizer when the DSM input is close to full scale, resulting in a rapidly increasing THD+N due to the clipping error in the high-P_OUT region. As such, the maximum P_OUT with THD+N<1 % is decreased, which squanders the boosted V_PVDD. In addition to the DSM-shaped noise, the PCM-to-PWM converter's clock (CLK) jitter noise is more significant when PWM pulses are narrower in the low-P_OUT region. As for the medium-P_OUT region, where the minimum THD+N is usually located, the THD+N is dominated by the Class-D power-stage nonlinearities.
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U2 - 10.1109/ISSCC42614.2022.9731791
DO - 10.1109/ISSCC42614.2022.9731791
M3 - Conference contribution
AN - SCOPUS:85128281553
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 486
EP - 488
BT - 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Y2 - 20 February 2022 through 26 February 2022
ER -