A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth

Wei Te Lin; Tai-Haur Kuo

doi:10.1109/ISSCC.2013.6487821

A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth

Wei Te Lin, Tai-Haur Kuo

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

29 Citations (Scopus)

Abstract

Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at the widest possible signal bandwidth. However, the above performances are degraded by many nonlinear causes, e.g., parasitic capacitor-induced finite output impedance [1], current-source (CS) mismatch, and input-code dependent switching transients [2]. While CS mismatch and input-code dependent switching transients result in distortion tones, the parasitic capacitor-induced finite output impedance further limits the high-linearity bandwidth and causes the SFDR to drop at high signal frequencies. In addition, low power consumption and small area are important factors for low-power applications and reduced implementation cost, respectively.

Original language	English
Title of host publication	2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
Pages	474-475
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2013.6487821
Publication status	Published - 2013 Apr 29
Event	2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States Duration: 2013 Feb 17 → 2013 Feb 21

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	56
ISSN (Print)	0193-6530

Other

Other	2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
Country/Territory	United States
City	San Francisco, CA
Period	13-02-17 → 13-02-21

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/ISSCC.2013.6487821

Cite this

Lin, W. T., & Kuo, T-H. (2013). A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth. In 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers (pp. 474-475). [6487821] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56). https://doi.org/10.1109/ISSCC.2013.6487821

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abstract = "Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at the widest possible signal bandwidth. However, the above performances are degraded by many nonlinear causes, e.g., parasitic capacitor-induced finite output impedance [1], current-source (CS) mismatch, and input-code dependent switching transients [2]. While CS mismatch and input-code dependent switching transients result in distortion tones, the parasitic capacitor-induced finite output impedance further limits the high-linearity bandwidth and causes the SFDR to drop at high signal frequencies. In addition, low power consumption and small area are important factors for low-power applications and reduced implementation cost, respectively.",

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Lin, WT & Kuo, T-H 2013, A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth. in 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers., 6487821, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 56, pp. 474-475, 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013, San Francisco, CA, United States, 13-02-17. https://doi.org/10.1109/ISSCC.2013.6487821

A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth. / Lin, Wei Te; Kuo, Tai-Haur.

2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. 2013. p. 474-475 6487821 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at the widest possible signal bandwidth. However, the above performances are degraded by many nonlinear causes, e.g., parasitic capacitor-induced finite output impedance [1], current-source (CS) mismatch, and input-code dependent switching transients [2]. While CS mismatch and input-code dependent switching transients result in distortion tones, the parasitic capacitor-induced finite output impedance further limits the high-linearity bandwidth and causes the SFDR to drop at high signal frequencies. In addition, low power consumption and small area are important factors for low-power applications and reduced implementation cost, respectively.

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A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth

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