TY - GEN
T1 - A 12TOPS/W Computing-in-Memory Accelerator for Convolutional Neural Networks
AU - Fu, Jun Hui
AU - Chang, Soon Jyh
N1 - Funding Information:
This work was supported in part by Ministry of Science and Technology of Taiwan under grant MOST-110-2218-E-006-021, and in part by QualComm Tech., Inc., under Contract NAT-408931.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents a charge redistribution based computing-in-memory (CIM) accelerator for convolutional neural networks (CNNs). This CIM macro adopts 9T static random access memory (SRAM) with a read-decoupled port to avoid read-disturbing and perform the analog computation for further diminishing the energy consumption per arithmetic operation. Weighted capacitor switching technique is proposed to achieve a better linearity performance than conventional current charging/discharging scheme and reduce the number of analog-to-digital converters (ADC). Moreover, low multiply-accumulate (MAC) value skipping technique is also proposed to enhance the speed and reduce the power consumption of the CIM macro by skipping the first few bits during the analog-to-digital conversion. The proposed CIM macro was fabricated in TSMC 40-nm CMOS process. Measurement results show that the proof-of-concept prototype achieves an energy efficiency of 12.02 TOPS/W under 8-bit input and 8-bit weight resolution.
AB - This paper presents a charge redistribution based computing-in-memory (CIM) accelerator for convolutional neural networks (CNNs). This CIM macro adopts 9T static random access memory (SRAM) with a read-decoupled port to avoid read-disturbing and perform the analog computation for further diminishing the energy consumption per arithmetic operation. Weighted capacitor switching technique is proposed to achieve a better linearity performance than conventional current charging/discharging scheme and reduce the number of analog-to-digital converters (ADC). Moreover, low multiply-accumulate (MAC) value skipping technique is also proposed to enhance the speed and reduce the power consumption of the CIM macro by skipping the first few bits during the analog-to-digital conversion. The proposed CIM macro was fabricated in TSMC 40-nm CMOS process. Measurement results show that the proof-of-concept prototype achieves an energy efficiency of 12.02 TOPS/W under 8-bit input and 8-bit weight resolution.
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U2 - 10.1109/ISCAS48785.2022.9937467
DO - 10.1109/ISCAS48785.2022.9937467
M3 - Conference contribution
AN - SCOPUS:85142525332
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 586
EP - 589
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Y2 - 27 May 2022 through 1 June 2022
ER -
