TY - JOUR
T1 - A 14-bit low power 2-ms/s sar adc with residue oversampling*
AU - Huang, Sheng Wen
AU - Chang, Li Jen
AU - Chang, Soon Jyh
N1 - Funding Information:
This work was supported by Ministry of Science and Technology of Taiwan under grant MOST-108-2218-E-006-014.This work was supported by Ministry of Science and Technology of Taiwan under grant MOST-108-2218-E-006-014. The authors also thank the fabrication and measurement supports of the Taiwan Semiconductor Research Institute (TSRI).
Publisher Copyright:
© 2020, Chinese Institute of Electrical Engineering. All rights reserved.
PY - 2020/6
Y1 - 2020/6
N2 - This paper presents a 2-MS/s 14-bit successive-approximation register (SAR) analog-to-digital converter (ADC) in 40 nm CMOS technology. For high resolution and low power requirements, the ADC adopts residue oversampling and Detect-and-Skip (DAS) techniques. Residue oversampling is able to reduce capacitor mismatch and noise. Therefore, the integral nonlinearity (INL), and differential nonlinearity (DNL) are diminished, and signal-to-noise ratio (SNDR) is enhanced. Besides, Detect-and-Skip (DAS) is adopted to decrease capacitor switching power and capacitor mismatch. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 2-MS/s sampling rates and 100-kS/s input frequency, the measured SNDR is 68.04dB. Static performance shows that DNL and INL are +2.31/-0.92 and +3.67/-3.92LSB, re-spectively.
AB - This paper presents a 2-MS/s 14-bit successive-approximation register (SAR) analog-to-digital converter (ADC) in 40 nm CMOS technology. For high resolution and low power requirements, the ADC adopts residue oversampling and Detect-and-Skip (DAS) techniques. Residue oversampling is able to reduce capacitor mismatch and noise. Therefore, the integral nonlinearity (INL), and differential nonlinearity (DNL) are diminished, and signal-to-noise ratio (SNDR) is enhanced. Besides, Detect-and-Skip (DAS) is adopted to decrease capacitor switching power and capacitor mismatch. The proof-of-concept prototype was fabricated in TSMC 40-nm CMOS technology. At 2-MS/s sampling rates and 100-kS/s input frequency, the measured SNDR is 68.04dB. Static performance shows that DNL and INL are +2.31/-0.92 and +3.67/-3.92LSB, re-spectively.
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U2 - 10.6329/CIEE.202006_27(3).0003
DO - 10.6329/CIEE.202006_27(3).0003
M3 - Article
AN - SCOPUS:85091721706
VL - 27
SP - 105
EP - 114
JO - International Journal of Electrical Engineering
JF - International Journal of Electrical Engineering
SN - 1812-3031
IS - 3
ER -