A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique

Jia Ching Wang, Tsung Chih Hung, Tai-Haur Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 15-bit pipelined ADC using the averaging correlated level shifting (Averaging-CLS) technique for reducing finite opamp gain error and opamp thermal noise. Adopting the Averaging-CLS technique enables an ADC to use a medium-accuracy amplifier structure in a high-resolution ADC. Furthermore, the front-end sample-and-hold amplifier (SHA) is removed to reduce power consumption and cost. The 15-bit pipelined ADC was fabricated by 90 nm CMOS. The measured peak SNDR achieves 73.7 dB at a 20 MS/s sampling rate and the ADC consumes 4.7 mW, leading to the Walden and Schreier Figure-of-Merits of 59.4 fJ/conv.-step and 167 dB, respectively.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
Publication statusPublished - 2019 Apr 1
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 2019 Apr 222019 Apr 25

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
CountryTaiwan
CityHsinchu
Period19-04-2219-04-25

Fingerprint

Operational amplifiers
amplifiers
Thermal noise
thermal noise
figure of merit
CMOS
Electric power utilization
sampling
Sampling
costs
high resolution
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Wang, J. C., Hung, T. C., & Kuo, T-H. (2019). A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741986] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741986
Wang, Jia Ching ; Hung, Tsung Chih ; Kuo, Tai-Haur. / A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).
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abstract = "This paper presents a 15-bit pipelined ADC using the averaging correlated level shifting (Averaging-CLS) technique for reducing finite opamp gain error and opamp thermal noise. Adopting the Averaging-CLS technique enables an ADC to use a medium-accuracy amplifier structure in a high-resolution ADC. Furthermore, the front-end sample-and-hold amplifier (SHA) is removed to reduce power consumption and cost. The 15-bit pipelined ADC was fabricated by 90 nm CMOS. The measured peak SNDR achieves 73.7 dB at a 20 MS/s sampling rate and the ADC consumes 4.7 mW, leading to the Walden and Schreier Figure-of-Merits of 59.4 fJ/conv.-step and 167 dB, respectively.",
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Wang, JC, Hung, TC & Kuo, T-H 2019, A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741986, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 19-04-22. https://doi.org/10.1109/VLSI-DAT.2019.8741986

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. / Wang, Jia Ching; Hung, Tsung Chih; Kuo, Tai-Haur.

2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741986 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Wang JC, Hung TC, Kuo T-H. A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8741986. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). https://doi.org/10.1109/VLSI-DAT.2019.8741986