A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique

Jia Ching Wang; Tsung Chih Hung; Tai Haur Kuo

doi:10.1109/VLSI-DAT.2019.8741986

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique

Jia Ching Wang, Tsung Chih Hung, Tai Haur Kuo

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a 15-bit pipelined ADC using the averaging correlated level shifting (Averaging-CLS) technique for reducing finite opamp gain error and opamp thermal noise. Adopting the Averaging-CLS technique enables an ADC to use a medium-accuracy amplifier structure in a high-resolution ADC. Furthermore, the front-end sample-and-hold amplifier (SHA) is removed to reduce power consumption and cost. The 15-bit pipelined ADC was fabricated by 90 nm CMOS. The measured peak SNDR achieves 73.7 dB at a 20 MS/s sampling rate and the ADC consumes 4.7 mW, leading to the Walden and Schreier Figure-of-Merits of 59.4 fJ/conv.-step and 167 dB, respectively.

Original language	English
Title of host publication	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728106557
DOIs	https://doi.org/10.1109/VLSI-DAT.2019.8741986
Publication status	Published - 2019 Apr
Event	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan Duration: 2019 Apr 22 → 2019 Apr 25

Publication series

Name	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/Territory	Taiwan
City	Hsinchu
Period	19-04-22 → 19-04-25

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/VLSI-DAT.2019.8741986

Cite this

Wang, J. C., Hung, T. C., & Kuo, T. H. (2019). A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 Article 8741986 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741986

Wang, Jia Ching ; Hung, Tsung Chih ; Kuo, Tai Haur. / A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

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title = "A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique",

abstract = "This paper presents a 15-bit pipelined ADC using the averaging correlated level shifting (Averaging-CLS) technique for reducing finite opamp gain error and opamp thermal noise. Adopting the Averaging-CLS technique enables an ADC to use a medium-accuracy amplifier structure in a high-resolution ADC. Furthermore, the front-end sample-and-hold amplifier (SHA) is removed to reduce power consumption and cost. The 15-bit pipelined ADC was fabricated by 90 nm CMOS. The measured peak SNDR achieves 73.7 dB at a 20 MS/s sampling rate and the ADC consumes 4.7 mW, leading to the Walden and Schreier Figure-of-Merits of 59.4 fJ/conv.-step and 167 dB, respectively.",

author = "Wang, {Jia Ching} and Hung, {Tsung Chih} and Kuo, {Tai Haur}",

year = "2019",

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doi = "10.1109/VLSI-DAT.2019.8741986",

language = "English",

series = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

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note = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 ; Conference date: 22-04-2019 Through 25-04-2019",

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Wang, JC, Hung, TC & Kuo, TH 2019, A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741986, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 19-04-22. https://doi.org/10.1109/VLSI-DAT.2019.8741986

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. / Wang, Jia Ching; Hung, Tsung Chih; Kuo, Tai Haur.
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741986 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Wang JC, Hung TC, Kuo TH. A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8741986. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). doi: 10.1109/VLSI-DAT.2019.8741986

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with averaging correlated level shifting technique

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