A 1.5-bit/stage pipeline ADC with FFT-based calibration method

Ming Chun Liang, Cheng Han Hsieh, Shuenn-Yuh Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A fast Fourier transform-based (FFT-based) foreground digital calibration method for multistage pipeline analog-to-digital converter (ADC) is proposed in this paper. The calibration method can overcome the capacitor mismatch and finite gain of the operational amplifier (OPAMP). Given that the capacitor mismatch and finite OPAMP gain cause the radix of all the stages of multistage pipeline ADC to become unequal to 2n, the FFT processor can be adopted to evaluate the real radixes of all the stages and generate new digital output to compensate the error caused by these nonideal effects. Moreover, because capacitor mismatch and the finite gain of OPAMP can be compensated, low-gain OPAMP can be used in high-performance ADC to reduce the power dissipation, and the small capacitor can be adopted to save the area. An example of a 10-bit 1.5-bit/stage pipelined ADC with only an 8-bit circuit performance is implemented in 0.18 μm TSMC CMOS process. The circuit measurement result reveals that the signal-to-noise-and-distortion ratio (SNDR) of 51.03 dB with 11-dB improvement after calibration can be achieved at the sample rate of 1 MHz.

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages2042-2045
Number of pages4
DOIs
Publication statusPublished - 2013 Sep 9
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 2013 May 192013 May 23

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period13-05-1913-05-23

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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  • Cite this

    Liang, M. C., Hsieh, C. H., & Lee, S-Y. (2013). A 1.5-bit/stage pipeline ADC with FFT-based calibration method. In 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 (pp. 2042-2045). [6572273] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2013.6572273