TY - JOUR
T1 - A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling
AU - Bashirullah, Rizwan
AU - Liu, Wentai
AU - Cavin, Ralph
AU - Edwards, Dale
PY - 2006/2
Y1 - 2006/2
N2 - This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 μm CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66 % over voltage-mode (VM) sensing, respectively.
AB - This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 μm CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66 % over voltage-mode (VM) sensing, respectively.
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U2 - 10.1109/JSSC.2005.862351
DO - 10.1109/JSSC.2005.862351
M3 - Article
AN - SCOPUS:31644437355
SN - 0018-9200
VL - 41
SP - 461
EP - 473
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
ER -