A 1.6-Gs/s 8b flash-SAR time-interleaved ADC with top-plate residue based gain calibration

Che Wei Hsu, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timing-skew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.

Original languageEnglish
Title of host publication2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728192017
DOIs
Publication statusPublished - 2021
Event53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of
Duration: 2021 May 222021 May 28

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2021-May
ISSN (Print)0271-4310

Conference

Conference53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/TerritoryKorea, Republic of
CityDaegu
Period21-05-2221-05-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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