TY - GEN
T1 - A 1.6-Gs/s 8b flash-SAR time-interleaved ADC with top-plate residue based gain calibration
AU - Hsu, Che Wei
AU - Chang, Soon Jyh
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Ministry of Science and Technology of Taiwan under grant MOST-108-2218-E-006-014.
Publisher Copyright:
© 2021 IEEE
PY - 2021
Y1 - 2021
N2 - This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timing-skew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.
AB - This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timing-skew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.
UR - http://www.scopus.com/inward/record.url?scp=85109019632&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85109019632&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401198
DO - 10.1109/ISCAS51556.2021.9401198
M3 - Conference contribution
AN - SCOPUS:85109019632
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Y2 - 22 May 2021 through 28 May 2021
ER -