A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications

Anh Tuan Do, Chun Kit Lam, Yung Sern Tan, Kiat Seng Yeo, Jia Hao Cheong, Xiaodan Zou, Lei Yao, Kuang-Wei Cheng, Minkyu Je

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.

Original languageEnglish
Title of host publication2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
Pages525-528
Number of pages4
DOIs
Publication statusPublished - 2012 Nov 7
Event2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 - Montreal, QC, Canada
Duration: 2012 Jun 172012 Jun 20

Publication series

Name2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012

Other

Other2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
CountryCanada
CityMontreal, QC
Period12-06-1712-06-20

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Control and Systems Engineering

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