TY - GEN
T1 - A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications
AU - Do, Anh Tuan
AU - Lam, Chun Kit
AU - Tan, Yung Sern
AU - Yeo, Kiat Seng
AU - Cheong, Jia Hao
AU - Zou, Xiaodan
AU - Yao, Lei
AU - Cheng, Kuang-Wei
AU - Je, Minkyu
PY - 2012/11/7
Y1 - 2012/11/7
N2 - This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.
AB - This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.
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U2 - 10.1109/NEWCAS.2012.6329072
DO - 10.1109/NEWCAS.2012.6329072
M3 - Conference contribution
AN - SCOPUS:84868272462
SN - 9781467308595
T3 - 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
SP - 525
EP - 528
BT - 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
T2 - 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
Y2 - 17 June 2012 through 20 June 2012
ER -