Abstract
This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.
| Original language | English |
|---|---|
| Title of host publication | 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 |
| Pages | 525-528 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 - Montreal, QC, Canada Duration: 2012 Jun 17 → 2012 Jun 20 |
Other
| Other | 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012 |
|---|---|
| Country | Canada |
| City | Montreal, QC |
| Period | 12-06-17 → 12-06-20 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Control and Systems Engineering
Cite this
}
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications. / Do, Anh Tuan; Lam, Chun Kit; Tan, Yung Sern; Yeo, Kiat Seng; Cheong, Jia Hao; Zou, Xiaodan; Yao, Lei; Cheng, Kuang-Wei; Je, Minkyu.
2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012. 2012. p. 525-528 6329072.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications
AU - Do, Anh Tuan
AU - Lam, Chun Kit
AU - Tan, Yung Sern
AU - Yeo, Kiat Seng
AU - Cheong, Jia Hao
AU - Zou, Xiaodan
AU - Yao, Lei
AU - Cheng, Kuang-Wei
AU - Je, Minkyu
PY - 2012
Y1 - 2012
N2 - This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.
AB - This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.
UR - http://www.scopus.com/inward/record.url?scp=84868272462&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84868272462&partnerID=8YFLogxK
U2 - 10.1109/NEWCAS.2012.6329072
DO - 10.1109/NEWCAS.2012.6329072
M3 - Conference contribution
SN - 9781467308595
SP - 525
EP - 528
BT - 2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012
ER -