A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Ying Zu Lin, Chung-Ming Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

114 Citations (Scopus)

Abstract

This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Circuits, VLSIC 2010
Pages241-242
Number of pages2
DOIs
Publication statusPublished - 2010 Oct 22
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
Duration: 2010 Jun 162010 Jun 18

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country/TerritoryUnited States
CityHonolulu, HI
Period10-06-1610-06-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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