A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

Chun Cheng Liu; Soon-Jyh Chang; Guan Ying Huang; Ying Zu Lin; Chung-Ming Huang

doi:10.1109/VLSIC.2010.5560283

A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

Chun Cheng Liu, Soon-Jyh Chang, Guan Ying Huang, Ying Zu Lin, Chung-Ming Huang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

107 Citations (Scopus)

Abstract

This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

Original language	English
Title of host publication	2010 Symposium on VLSI Circuits, VLSIC 2010
Pages	241-242
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560283
Publication status	Published - 2010 Oct 22
Event	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States Duration: 2010 Jun 16 → 2010 Jun 18

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country	United States
City	Honolulu, HI
Period	10-06-16 → 10-06-18

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSIC.2010.5560283

Cite this

Liu, C. C., Chang, S-J., Huang, G. Y., Lin, Y. Z., & Huang, C-M. (2010). A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. In 2010 Symposium on VLSI Circuits, VLSIC 2010 (pp. 241-242). [5560283] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2010.5560283

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title = "A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS",

abstract = "This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.",

author = "Liu, {Chun Cheng} and Soon-Jyh Chang and Huang, {Guan Ying} and Lin, {Ying Zu} and Chung-Ming Huang",

year = "2010",

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doi = "10.1109/VLSIC.2010.5560283",

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series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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Liu, CC, Chang, S-J, Huang, GY, Lin, YZ & Huang, C-M 2010, A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. in 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560283, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 241-242, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 10-06-16. https://doi.org/10.1109/VLSIC.2010.5560283

A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS. / Liu, Chun Cheng; Chang, Soon-Jyh; Huang, Guan Ying; Lin, Ying Zu; Huang, Chung-Ming.

2010 Symposium on VLSI Circuits, VLSIC 2010. 2010. p. 241-242 5560283 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.

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