A 2-gs/s 6-bit flash adc with offset calibration

Ying Zu Lin; Cheng Wu Lin; Soon Jyh Chang

doi:10.1109/ASSCC.2008.4708808

A 2-gs/s 6-bit flash adc with offset calibration

Ying Zu Lin, Cheng Wu Lin, Soon Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.

Original language	English
Title of host publication	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages	385-388
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2008.4708808
Publication status	Published - 2008
Event	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan Duration: 2008 Nov 3 → 2008 Nov 5

Publication series

Name	Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other	2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/Territory	Japan
City	Fukuoka
Period	08-11-03 → 08-11-05

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2008.4708808

Cite this

@inproceedings{35c3e4a5000941419b19c4ec3b1bd572,

title = "A 2-gs/s 6-bit flash adc with offset calibration",

abstract = "A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.",

author = "Lin, {Ying Zu} and Lin, {Cheng Wu} and Chang, {Soon Jyh}",

year = "2008",

doi = "10.1109/ASSCC.2008.4708808",

language = "English",

isbn = "9781424426058",

series = "Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008",

pages = "385--388",

booktitle = "Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008",

note = "2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 ; Conference date: 03-11-2008 Through 05-11-2008",

}

Lin, YZ, Lin, CW & Chang, SJ 2008, A 2-gs/s 6-bit flash adc with offset calibration. in Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008., 4708808, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, pp. 385-388, 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008, Fukuoka, Japan, 08-11-03. https://doi.org/10.1109/ASSCC.2008.4708808

TY - GEN

T1 - A 2-gs/s 6-bit flash adc with offset calibration

AU - Lin, Ying Zu

AU - Lin, Cheng Wu

AU - Chang, Soon Jyh

PY - 2008

Y1 - 2008

N2 - A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.

AB - A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.

UR - http://www.scopus.com/inward/record.url?scp=67649983275&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67649983275&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2008.4708808

DO - 10.1109/ASSCC.2008.4708808

M3 - Conference contribution

AN - SCOPUS:67649983275

SN - 9781424426058

T3 - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

SP - 385

EP - 388

BT - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

T2 - 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Y2 - 3 November 2008 through 5 November 2008

ER -

A 2-gs/s 6-bit flash adc with offset calibration

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