A 2-gs/s 6-bit flash adc with offset calibration

Ying Zu Lin, Cheng Wu Lin, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-μm CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages385-388
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Publication series

NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Country/TerritoryJapan
CityFukuoka
Period08-11-0308-11-05

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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