A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

Chia Hsin Lee, Chih Huei Hou, Chun Po Huang, Soon Jyh Chang, Yuan Ta Hsieh, Ying Zong Juang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a single-channel 2.5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with conventional 2.5-bit/cycle SAR ADC, the proposed technique can save one sub-digital-to-analog converter (sub-DAC) and reduce the requirement on resolution for the other sub-DACs. Besides, the proposed digital code error correction provides a wider error tolerance range. The proposed ADC was fabricated in TSMC 90-nm CMOS process. At 1-V supply and 160 MS/s, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.06 dB with power consumption of 1.97 mW.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
Publication statusPublished - 2016 May 31
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 2016 Apr 252016 Apr 27

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period16-04-2516-04-27

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

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