A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS

Hugo Cruz; Hong Yi Huang; Shueen Yu Lee; Ching Hsing Luo

doi:10.1109/VLSI-DAT.2015.7114501

A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS

Hugo Cruz, Hong Yi Huang, Shueen Yu Lee, Ching Hsing Luo

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm².

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114501
Publication status	Published - 2015 May 28
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 2015 Apr 27 → 2015 Apr 29

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Other

Other	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	15-04-27 → 15-04-29

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-DAT.2015.7114501

Cite this

Cruz, H., Huang, H. Y., Lee, S. Y., & Luo, C. H. (2015). A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 Article 7114501 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114501

Cruz, Hugo ; Huang, Hong Yi ; Lee, Shueen Yu et al. / A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

@inproceedings{e86d45ae0d56474fbdba2d64e8d86e83,

title = "A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS",

abstract = "A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.",

author = "Hugo Cruz and Huang, {Hong Yi} and Lee, {Shueen Yu} and Luo, {Ching Hsing}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114501",

language = "English",

series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

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Cruz, H, Huang, HY, Lee, SY & Luo, CH 2015, A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114501, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 15-04-27. https://doi.org/10.1109/VLSI-DAT.2015.7114501

A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. / Cruz, Hugo; Huang, Hong Yi; Lee, Shueen Yu et al.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114501 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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AU - Cruz, Hugo

AU - Huang, Hong Yi

AU - Lee, Shueen Yu

AU - Luo, Ching Hsing

PY - 2015/5/28

Y1 - 2015/5/28

N2 - A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.

AB - A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.

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M3 - Conference contribution

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BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Y2 - 27 April 2015 through 29 April 2015

ER -

Cruz H, Huang HY, Lee SY, Luo CH. A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7114501. (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). doi: 10.1109/VLSI-DAT.2015.7114501

A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS

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