A 250-MHz Wave Pipelined Adder in 2-µm CMOS

Wentai Liu, Ralph K. Cavin, David Fan, William J. Farlow, C. Thomas Gray, Thomas A. Hughes

Research output: Contribution to journalArticlepeer-review

35 Citations (Scopus)

Abstract

Wave pipelining (also known as maximal rate pipelining) is a timing methodology used in digital systems to increase the number of effective pipelined stages without increasing the number of physical registers in the system. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic. Achieving a high degree of wave pipelining in CMOS technology requires careful study of delay balancing technique involving circuit design, layout method, and testing structure. A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-µm technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation.

Original languageEnglish
Pages (from-to)1117-1128
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number9
DOIs
Publication statusPublished - 1994 Sept

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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