A 3D hybrid cache design for CMP architecture for data-intensive applications

Ing-Chao Lin; Jeng Nian Chiou; Yun Kae Law

doi:10.1201/b21235

A 3D hybrid cache design for CMP architecture for data-intensive applications

Ing-Chao Lin, Jeng Nian Chiou, Yun Kae Law

Department of Computer Science and Information Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.

Original language	English
Title of host publication	High Performance Computing for Big Data
Subtitle of host publication	Methodologies and Applications
Publisher	CRC Press
Pages	59-80
Number of pages	22
ISBN (Electronic)	9781498784009
ISBN (Print)	9781498783996
DOIs	https://doi.org/10.1201/b21235
Publication status	Published - 2017 Jan 1

All Science Journal Classification (ASJC) codes

General Computer Science
Economics, Econometrics and Finance(all)
General Business,Management and Accounting

Access to Document

10.1201/b21235

Cite this

@inbook{27f5490783e249718afd2ce3016adec5,

title = "A 3D hybrid cache design for CMP architecture for data-intensive applications",

abstract = "With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.",

author = "Ing-Chao Lin and Chiou, {Jeng Nian} and Law, {Yun Kae}",

year = "2017",

month = jan,

day = "1",

doi = "10.1201/b21235",

language = "English",

isbn = "9781498783996",

pages = "59--80",

booktitle = "High Performance Computing for Big Data",

publisher = "CRC Press",

}

TY - CHAP

T1 - A 3D hybrid cache design for CMP architecture for data-intensive applications

AU - Lin, Ing-Chao

AU - Chiou, Jeng Nian

AU - Law, Yun Kae

PY - 2017/1/1

Y1 - 2017/1/1

N2 - With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.

AB - With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.

UR - http://www.scopus.com/inward/record.url?scp=85052681135&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85052681135&partnerID=8YFLogxK

U2 - 10.1201/b21235

DO - 10.1201/b21235

M3 - Chapter

AN - SCOPUS:85052681135

SN - 9781498783996

SP - 59

EP - 80

BT - High Performance Computing for Big Data

PB - CRC Press

ER -

A 3D hybrid cache design for CMP architecture for data-intensive applications

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this