A 3D hybrid cache design for CMP architecture for data-intensive applications

Ing-Chao Lin, Jeng Nian Chiou, Yun Kae Law

Research output: Chapter in Book/Report/Conference proceedingChapter


With the advance of CMOS technology, CPU performance has been improved by increasing frequency. However, the performance improvement for a single-core processor has reached a 60bottleneck due to chip power and heat removal limitations. To overcome these problems, chip multiprocessors (CMPs) have gradually replaced single-core processors, and the number of cores in CMPs is expected to continue to grow. A processor integrating 80 cores has been demonstrated by Intel [1]. In CMP architecture, the last level cache (LLC) is shared by multicore processors and has a significant influence on performance. Therefore, as the CMP architecture has become more widely used, LLC-related research has drawn increased attention.

Original languageEnglish
Title of host publicationHigh Performance Computing for Big Data
Subtitle of host publicationMethodologies and Applications
PublisherCRC Press
Number of pages22
ISBN (Electronic)9781498784009
ISBN (Print)9781498783996
Publication statusPublished - 2017 Jan 1

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Economics, Econometrics and Finance(all)
  • Business, Management and Accounting(all)


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