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A 3D hybrid cache design for CMP architecture for data-intensive applications
Ing-Chao Lin
, Jeng Nian Chiou
, Yun Kae Law
Department of Computer Science and Information Engineering
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Keyphrases
Chip multiprocessor
100%
Data-intensive Applications
100%
3D Hybrid
100%
Cache Design
100%
Hybrid Cache
100%
Multiprocessor Architecture
100%
Last-level Cache
40%
Core Processor
40%
Performance Improvement
20%
CMOS Technology
20%
Multicore Processors
20%
CPU Utilization
20%
Intel
20%
Heat Removal
20%
Number of Cores
20%
Computer Science
Chip Multiprocessor
100%
data-intensive application
100%
Core Processor
40%
Performance Improvement
20%
Multicore Processor
20%