TY - GEN
T1 - A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique
AU - Chao, I. Jen
AU - Kuo, Chia Ming
AU - Liu, Bin-Da
AU - Huang, Chun Yueh
AU - Chang, Soon-Jyh
PY - 2013/9/9
Y1 - 2013/9/9
N2 - This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm 2.
AB - This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm 2.
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U2 - 10.1109/ISCAS.2013.6572263
DO - 10.1109/ISCAS.2013.6572263
M3 - Conference contribution
AN - SCOPUS:84883365241
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2002
EP - 2005
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -