A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique

I. Jen Chao, Chia Ming Kuo, Bin-Da Liu, Chun Yueh Huang, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm 2.

Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages2002-2005
Number of pages4
DOIs
Publication statusPublished - 2013 Sep 9
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 2013 May 192013 May 23

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CountryChina
CityBeijing
Period13-05-1913-05-23

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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