A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

Tsung-chih Hung, Tai-haur Kuo

Research output: Contribution to conferencePaper

Original languageEnglish
Pages1-4
DOIs
Publication statusPublished - 2019 Apr
Event2019 IEEE Custom Integrated Circuits Conference (CICC) - Austin, TX, USA
Duration: 2019 Apr 142019 Apr 17

Conference

Conference2019 IEEE Custom Integrated Circuits Conference (CICC)
Period19-04-1419-04-17

Cite this

@conference{b28ef9fc4c2043879959cc01290f6dd8,
title = "A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth",
author = "Tsung-chih Hung and Tai-haur Kuo",
year = "2019",
month = "4",
doi = "10.1109/CICC.2019.8780368",
language = "English",
pages = "1--4",
note = "2019 IEEE Custom Integrated Circuits Conference (CICC) ; Conference date: 14-04-2019 Through 17-04-2019",

}

A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth. / Hung, Tsung-chih; Kuo, Tai-haur.

2019. 1-4 Paper presented at 2019 IEEE Custom Integrated Circuits Conference (CICC), .

Research output: Contribution to conferencePaper

TY - CONF

T1 - A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

AU - Hung, Tsung-chih

AU - Kuo, Tai-haur

PY - 2019/4

Y1 - 2019/4

U2 - 10.1109/CICC.2019.8780368

DO - 10.1109/CICC.2019.8780368

M3 - Paper

SP - 1

EP - 4

ER -