A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

Tsung-chih Hung; Tai-haur Kuo

doi:10.1109/CICC.2019.8780368

A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

Tsung-chih Hung, Tai-haur Kuo

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Original language	English
Pages	1-4
DOIs	https://doi.org/10.1109/CICC.2019.8780368
Publication status	Published - 2019 Apr
Event	2019 IEEE Custom Integrated Circuits Conference (CICC) - Austin, TX, USA Duration: 2019 Apr 14 → 2019 Apr 17

Conference

Conference	2019 IEEE Custom Integrated Circuits Conference (CICC)
Period	19-04-14 → 19-04-17

Access to Document

10.1109/CICC.2019.8780368

https://ieeexplore.ieee.org/document/8780368/

Cite this

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title = "A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth",

author = "Tsung-chih Hung and Tai-haur Kuo",

year = "2019",

month = apr,

doi = "10.1109/CICC.2019.8780368",

language = "English",

pages = "1--4",

note = "2019 IEEE Custom Integrated Circuits Conference (CICC) ; Conference date: 14-04-2019 Through 17-04-2019",

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