A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique

Tsung Chih Hung, Tai Haur Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper proposes an averaging correlated level shifting (Averaging-CLS) technique as a switched-capacitor amplification technique for reducing finite opamp gain error. The Averaging-CLS inverts the finite opamp gain error in the second amplifying phase and then averages it with that in the first amplifying phase. With Averaging-CLS, a high-resolution pipelined ADC can employ medium-accuracy high-efficiency ring amplifiers, which lowers the power consumption and cost of the ADC. Compared with conventional CLS, Averaging-CLS halves the sampling capacitance under the same SNR requirement. A 15-bit pipelined ADC, which operates from a 1.2 V power supply and utilizes an input range of 2.2 V peak-to-peak differential, was realized in a 90 nm CMOS technology. The ADC achieves a 74 dB peak SNDR at 22.5 MS/s conversion rate and consumes 4.86 mW, resulting in the Walden and Schreier Figure-of-Merits of 52.7fJ/conv.-step and 167.6dB, respectively.

Original languageEnglish
Title of host publication2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages161-164
Number of pages4
ISBN (Electronic)9781509037001
DOIs
Publication statusPublished - 2017 Feb 6
Event12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan
Duration: 2016 Nov 72016 Nov 9

Publication series

Name2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

Other

Other12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016
CountryJapan
CityToyama
Period16-11-0716-11-09

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique'. Together they form a unique fingerprint.

Cite this