A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique

Tsung Chih Hung; Tai Haur Kuo

doi:10.1109/ASSCC.2016.7844160

A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique

Tsung Chih Hung, Tai Haur Kuo

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper proposes an averaging correlated level shifting (Averaging-CLS) technique as a switched-capacitor amplification technique for reducing finite opamp gain error. The Averaging-CLS inverts the finite opamp gain error in the second amplifying phase and then averages it with that in the first amplifying phase. With Averaging-CLS, a high-resolution pipelined ADC can employ medium-accuracy high-efficiency ring amplifiers, which lowers the power consumption and cost of the ADC. Compared with conventional CLS, Averaging-CLS halves the sampling capacitance under the same SNR requirement. A 15-bit pipelined ADC, which operates from a 1.2 V power supply and utilizes an input range of 2.2 V peak-to-peak differential, was realized in a 90 nm CMOS technology. The ADC achieves a 74 dB peak SNDR at 22.5 MS/s conversion rate and consumes 4.86 mW, resulting in the Walden and Schreier Figure-of-Merits of 52.7fJ/conv.-step and 167.6dB, respectively.

Original language	English
Title of host publication	2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	161-164
Number of pages	4
ISBN (Electronic)	9781509037001
DOIs	https://doi.org/10.1109/ASSCC.2016.7844160
Publication status	Published - 2017 Feb 6
Event	12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Toyama, Japan Duration: 2016 Nov 7 → 2016 Nov 9

Publication series

Name	2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

Other

Other	12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016
Country	Japan
City	Toyama
Period	16-11-07 → 16-11-09

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Hardware and Architecture

Access to Document

10.1109/ASSCC.2016.7844160

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Hung, T. C., & Kuo, T. H. (2017). A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings (pp. 161-164). [7844160] (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2016.7844160

Hung, Tsung Chih ; Kuo, Tai Haur. / A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 161-164 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings).

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abstract = "This paper proposes an averaging correlated level shifting (Averaging-CLS) technique as a switched-capacitor amplification technique for reducing finite opamp gain error. The Averaging-CLS inverts the finite opamp gain error in the second amplifying phase and then averages it with that in the first amplifying phase. With Averaging-CLS, a high-resolution pipelined ADC can employ medium-accuracy high-efficiency ring amplifiers, which lowers the power consumption and cost of the ADC. Compared with conventional CLS, Averaging-CLS halves the sampling capacitance under the same SNR requirement. A 15-bit pipelined ADC, which operates from a 1.2 V power supply and utilizes an input range of 2.2 V peak-to-peak differential, was realized in a 90 nm CMOS technology. The ADC achieves a 74 dB peak SNDR at 22.5 MS/s conversion rate and consumes 4.86 mW, resulting in the Walden and Schreier Figure-of-Merits of 52.7fJ/conv.-step and 167.6dB, respectively.",

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Hung, TC & Kuo, TH 2017, A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. in 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings., 7844160, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 161-164, 12th IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, 16-11-07. https://doi.org/10.1109/ASSCC.2016.7844160

A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. / Hung, Tsung Chih; Kuo, Tai Haur.

2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 161-164 7844160 (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper proposes an averaging correlated level shifting (Averaging-CLS) technique as a switched-capacitor amplification technique for reducing finite opamp gain error. The Averaging-CLS inverts the finite opamp gain error in the second amplifying phase and then averages it with that in the first amplifying phase. With Averaging-CLS, a high-resolution pipelined ADC can employ medium-accuracy high-efficiency ring amplifiers, which lowers the power consumption and cost of the ADC. Compared with conventional CLS, Averaging-CLS halves the sampling capacitance under the same SNR requirement. A 15-bit pipelined ADC, which operates from a 1.2 V power supply and utilizes an input range of 2.2 V peak-to-peak differential, was realized in a 90 nm CMOS technology. The ADC achieves a 74 dB peak SNDR at 22.5 MS/s conversion rate and consumes 4.86 mW, resulting in the Walden and Schreier Figure-of-Merits of 52.7fJ/conv.-step and 167.6dB, respectively.

AB - This paper proposes an averaging correlated level shifting (Averaging-CLS) technique as a switched-capacitor amplification technique for reducing finite opamp gain error. The Averaging-CLS inverts the finite opamp gain error in the second amplifying phase and then averages it with that in the first amplifying phase. With Averaging-CLS, a high-resolution pipelined ADC can employ medium-accuracy high-efficiency ring amplifiers, which lowers the power consumption and cost of the ADC. Compared with conventional CLS, Averaging-CLS halves the sampling capacitance under the same SNR requirement. A 15-bit pipelined ADC, which operates from a 1.2 V power supply and utilizes an input range of 2.2 V peak-to-peak differential, was realized in a 90 nm CMOS technology. The ADC achieves a 74 dB peak SNDR at 22.5 MS/s conversion rate and consumes 4.86 mW, resulting in the Walden and Schreier Figure-of-Merits of 52.7fJ/conv.-step and 167.6dB, respectively.

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BT - 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings

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Hung TC, Kuo TH. A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique. In 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 161-164. 7844160. (2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings). https://doi.org/10.1109/ASSCC.2016.7844160