A 5-bit 1 GSample/s two-stage ADC with a new flash folded architecture

Hung Yu Huang, Ying Zu Lin, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A 5-bit 1 GSample/s two-stage ADC is designed and simulated in TSMC 0.18-μm CMOS technology. The new architecture combines the characteristics of flash, subranging and folding ADC. The analog front-end of this work is the same as that of a typical flash ADC. By replacing folding amplifier with the current-mode multiplexer (MUX), cyclic thermometer code, the digital output of folding ADC, is obtained and frequency multiplication effect is avoided. Besides, the slow switching of the reference voltage range is also avoided. The number of the comparators is reduced to 16, and it is 32 typically. Operating at 1 GSample/s, the ENOB is 4.92 and 4.71 bit at input frequency 10 and 500 MHz, respectively. This ADC consumes 63mW from a 1.8 V supply, achieving FOMs of 2.4 pJ/conversion-step at 1 GSample/s.

Original languageEnglish
Title of host publicationTENCON 2007 - 2007 IEEE Region 10 Conference
DOIs
Publication statusPublished - 2007 Dec 1
EventIEEE Region 10 Conference, TENCON 2007 - Taipei, Taiwan
Duration: 2007 Oct 302007 Nov 2

Publication series

NameIEEE Region 10 Annual International Conference, Proceedings/TENCON

Other

OtherIEEE Region 10 Conference, TENCON 2007
CountryTaiwan
CityTaipei
Period07-10-3007-11-02

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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    Huang, H. Y., Lin, Y. Z., & Chang, S-J. (2007). A 5-bit 1 GSample/s two-stage ADC with a new flash folded architecture. In TENCON 2007 - 2007 IEEE Region 10 Conference [4428897] (IEEE Region 10 Annual International Conference, Proceedings/TENCON). https://doi.org/10.1109/TENCON.2007.4428897