A 5-bit 1 GSample/s two-stage ADC with a new flash folded architecture

Hung Yu Huang, Ying Zu Lin, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Fingerprint

Dive into the research topics of 'A 5-bit 1 GSample/s two-stage ADC with a new flash folded architecture'. Together they form a unique fingerprint.

Engineering & Materials Science