A 5-bit 1.35-GSPS DAC for UWB transceivers

Ren Li Chen, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper presents a low-power 5-bit 1.35-GSPS current-steering digital-to-analog converter (DAC) for ultrawideband (UWB) transceivers. A "3 (thermometer) + 2 (binary)" segmented structure is used for reaching a compromise between the circuit complexity and differential nonlinearity (DNL) error. To save the power consumption while maintaining the same output voltage swing, a bipolar current source cell is employed. Besides, a de-glitch latch is presented to reduce the clock feedthrough from the pass transistors. This DAC was implemented in a standard 0.18-μm 1P6M CMOS technology. The measured integral nonlinearity (INL) and the differential nonlinearity (DNL) are less than 0.04 LSB and 0.05 LSB, respectively. The spurious-free dynamic range (SFDR) is above 30 dB over the complete Nyquist band at a sampling rate of 1.35 GHz. The power consumption of this DAC is 9.7 mW. The active area of the circuit occupies 0.19 mm2.

Original languageEnglish
Title of host publicationProceedings - 2009 IEEE International Conference on Ultra-Wideband, ICUWB 2009
Pages175-179
Number of pages5
DOIs
Publication statusPublished - 2009 Dec 18
Event2009 IEEE International Conference on Ultra-Wideband, ICUWB 2009 - Vancouver, BC, Canada
Duration: 2009 Sep 92009 Sep 11

Publication series

NameProceedings - 2009 IEEE International Conference on Ultra-Wideband, ICUWB 2009

Other

Other2009 IEEE International Conference on Ultra-Wideband, ICUWB 2009
Country/TerritoryCanada
CityVancouver, BC
Period09-09-0909-09-11

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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