A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS

Ying Zu Lin, Yen Ting Liu, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V supply and occupies 0.16 mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages213-216
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
DOIs
Publication statusPublished - 2007 Jan 1
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: 2007 Sep 162007 Sep 19

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Other

Other29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
CountryUnited States
CitySan Jose
Period07-09-1607-09-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Lin, Y. Z., Liu, Y. T., & Chang, S. J. (2007). A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (pp. 213-216). [4405716] (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405716