Abstract
A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V supply and occupies 0.16 mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 213-216 |
| Number of pages | 4 |
| ISBN (Electronic) | 1424407869, 9781424407866 |
| DOIs | |
| Publication status | Published - 2007 |
| Event | 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States Duration: 2007 Sep 16 → 2007 Sep 19 |
Other
| Other | 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 |
|---|---|
| Country | United States |
| City | San Jose |
| Period | 07-09-16 → 07-09-19 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
}
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. / Lin, Ying Zu; Liu, Yen Ting; Chang, Soon-Jyh.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 213-216 4405716.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS
AU - Lin, Ying Zu
AU - Liu, Yen Ting
AU - Chang, Soon-Jyh
PY - 2007
Y1 - 2007
N2 - A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V supply and occupies 0.16 mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.
AB - A compact 5-bit flash ADC is designed and fabricated in TSMC 0.13-μm CMOS process. Resistive averaging network and interpolation are discussed and analyzed for power reduction. This proposed ADC consumes 180 mW from a 1.2 V supply and occupies 0.16 mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.51 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.
UR - http://www.scopus.com/inward/record.url?scp=67649925663&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649925663&partnerID=8YFLogxK
U2 - 10.1109/CICC.2007.4405716
DO - 10.1109/CICC.2007.4405716
M3 - Conference contribution
SP - 213
EP - 216
BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PB - Institute of Electrical and Electronics Engineers Inc.
ER -