A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS process

Ying Zu Lin, Soon-Jyh Chang, Yen Ting Liu

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-μm CMOS process. The proposed ADC consumes 180 mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2 GS/s, the ENOB is 4.44 bit and ERBW 1.65 GHz. At 4.2 GS/s, the ENOB is 4.20 bit and ERBW 1.75 GHz. This ADC achieves FOMs of 2.59 and 2.80 pJ/conversion-step at 3.2 and 4.2 GS/s, respectively.

Original languageEnglish
Pages (from-to)258-268
Number of pages11
JournalIEICE Transactions on Electronics
VolumeE92-C
Issue number2
DOIs
Publication statusPublished - 2009 Jan 1

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Digital to analog conversion
Electric power utilization
Interpolation
Chemical analysis

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Lin, Ying Zu ; Chang, Soon-Jyh ; Liu, Yen Ting. / A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS process. In: IEICE Transactions on Electronics. 2009 ; Vol. E92-C, No. 2. pp. 258-268.
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A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS process. / Lin, Ying Zu; Chang, Soon-Jyh; Liu, Yen Ting.

In: IEICE Transactions on Electronics, Vol. E92-C, No. 2, 01.01.2009, p. 258-268.

Research output: Contribution to journalArticle

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