Abstract
This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.
| Original language | English |
|---|---|
| Pages | 141-144 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 Dec 1 |
| Event | 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan Duration: 2012 Nov 12 → 2012 Nov 14 |
Other
| Other | 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 |
|---|---|
| Country | Japan |
| City | Kobe |
| Period | 12-11-12 → 12-11-14 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
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A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector. / Lee, Yen Long; Chang, Soon-Jyh; Chu, Rong Sing; Lin, Ying Zu; Chen, Yen Chi; Ren, Goh Jih; Huang, Chung-Ming.
2012. 141-144 Paper presented at 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, Japan.Research output: Contribution to conference › Paper
TY - CONF
T1 - A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector
AU - Lee, Yen Long
AU - Chang, Soon-Jyh
AU - Chu, Rong Sing
AU - Lin, Ying Zu
AU - Chen, Yen Chi
AU - Ren, Goh Jih
AU - Huang, Chung-Ming
PY - 2012/12/1
Y1 - 2012/12/1
N2 - This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.
AB - This paper presents a 5-Gb/s 1/4-rate clock and data recovery (CDR) circuit. The proposed dynamic stepwise bang-bang phase detector comprises the advantage of linear and bang-bang phase detectors. The CDR adjusts the charge pump currents and the interpolation weight of phase interpolators according to the phase error between input data and feedback clock. This CDR circuit was fabricated in TSMC 1P9M 90-nm CMOS technology. It consumes 16.8 mW from a 1.2-V supply and occupies an active area of 0.3 mm2. The measured peak-to-peak jitter and rms jitter of the recovered clock are 42.37 ps and 7.06 ps for a 5-Gb/s 27-1 PRBS, respectively. Moreover, the measured peak-to-peak jitter and rms jitter of the recovered data are 53.33 ps and 8.89 ps for a 5-Gb/s 27-1 PRBS, respectively.
UR - http://www.scopus.com/inward/record.url?scp=84881074272&partnerID=8YFLogxK
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U2 - 10.1109/IPEC.2012.6522645
DO - 10.1109/IPEC.2012.6522645
M3 - Paper
AN - SCOPUS:84881074272
SP - 141
EP - 144
ER -