A 5.7-GHz low-power and high-gain 0.18-μm CMOS double-balanced mixer for WLAN

C. H. Liao, Y. K. Chu, D. R. Huang, Huey-Ru Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presnts a low-power and high-gain 5.7 GHz CMOS double-balanced mixer for an IEEE 802.11a WLAN application. The RF input frequency of the mixer is 5.725-25GHz, LO is 5.265-5.325GHz, IF is at 480MHz. The mixwer is fabricated with the 0.18 μm 1P6M standard CMOS process. The die size is 0.627 × 0.649 mm2. The measurements are performed using an FR-4 PCB test fixture. The fabricated mixer exhibits a conversion gain of 11dB, noise figure of 12.8dB, and input P1dB -16.4dBm. The DC consumption current is 2.0 mA /1.0 mA for the core/buffer amplifier at VDD = 1.8 V.

Original languageEnglish
Title of host publication35th European Microwave Conference 2005 - Conference Proceedings
Pages1723-1726
Number of pages4
Volume3
DOIs
Publication statusPublished - 2005
Event2005 European Microwave Conference - Paris, France
Duration: 2005 Oct 42005 Oct 6

Other

Other2005 European Microwave Conference
CountryFrance
CityParis
Period05-10-0405-10-06

Fingerprint

Buffer amplifiers
Mixer circuits
Noise figure
Polychlorinated biphenyls
Wireless local area networks (WLAN)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Liao, C. H., Chu, Y. K., Huang, D. R., & Chuang, H-R. (2005). A 5.7-GHz low-power and high-gain 0.18-μm CMOS double-balanced mixer for WLAN. In 35th European Microwave Conference 2005 - Conference Proceedings (Vol. 3, pp. 1723-1726). [1610291] https://doi.org/10.1109/EUMC.2005.1610291
Liao, C. H. ; Chu, Y. K. ; Huang, D. R. ; Chuang, Huey-Ru. / A 5.7-GHz low-power and high-gain 0.18-μm CMOS double-balanced mixer for WLAN. 35th European Microwave Conference 2005 - Conference Proceedings. Vol. 3 2005. pp. 1723-1726
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abstract = "This paper presnts a low-power and high-gain 5.7 GHz CMOS double-balanced mixer for an IEEE 802.11a WLAN application. The RF input frequency of the mixer is 5.725-25GHz, LO is 5.265-5.325GHz, IF is at 480MHz. The mixwer is fabricated with the 0.18 μm 1P6M standard CMOS process. The die size is 0.627 × 0.649 mm2. The measurements are performed using an FR-4 PCB test fixture. The fabricated mixer exhibits a conversion gain of 11dB, noise figure of 12.8dB, and input P1dB -16.4dBm. The DC consumption current is 2.0 mA /1.0 mA for the core/buffer amplifier at VDD = 1.8 V.",
author = "Liao, {C. H.} and Chu, {Y. K.} and Huang, {D. R.} and Huey-Ru Chuang",
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Liao, CH, Chu, YK, Huang, DR & Chuang, H-R 2005, A 5.7-GHz low-power and high-gain 0.18-μm CMOS double-balanced mixer for WLAN. in 35th European Microwave Conference 2005 - Conference Proceedings. vol. 3, 1610291, pp. 1723-1726, 2005 European Microwave Conference, Paris, France, 05-10-04. https://doi.org/10.1109/EUMC.2005.1610291

A 5.7-GHz low-power and high-gain 0.18-μm CMOS double-balanced mixer for WLAN. / Liao, C. H.; Chu, Y. K.; Huang, D. R.; Chuang, Huey-Ru.

35th European Microwave Conference 2005 - Conference Proceedings. Vol. 3 2005. p. 1723-1726 1610291.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - This paper presnts a low-power and high-gain 5.7 GHz CMOS double-balanced mixer for an IEEE 802.11a WLAN application. The RF input frequency of the mixer is 5.725-25GHz, LO is 5.265-5.325GHz, IF is at 480MHz. The mixwer is fabricated with the 0.18 μm 1P6M standard CMOS process. The die size is 0.627 × 0.649 mm2. The measurements are performed using an FR-4 PCB test fixture. The fabricated mixer exhibits a conversion gain of 11dB, noise figure of 12.8dB, and input P1dB -16.4dBm. The DC consumption current is 2.0 mA /1.0 mA for the core/buffer amplifier at VDD = 1.8 V.

AB - This paper presnts a low-power and high-gain 5.7 GHz CMOS double-balanced mixer for an IEEE 802.11a WLAN application. The RF input frequency of the mixer is 5.725-25GHz, LO is 5.265-5.325GHz, IF is at 480MHz. The mixwer is fabricated with the 0.18 μm 1P6M standard CMOS process. The die size is 0.627 × 0.649 mm2. The measurements are performed using an FR-4 PCB test fixture. The fabricated mixer exhibits a conversion gain of 11dB, noise figure of 12.8dB, and input P1dB -16.4dBm. The DC consumption current is 2.0 mA /1.0 mA for the core/buffer amplifier at VDD = 1.8 V.

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Liao CH, Chu YK, Huang DR, Chuang H-R. A 5.7-GHz low-power and high-gain 0.18-μm CMOS double-balanced mixer for WLAN. In 35th European Microwave Conference 2005 - Conference Proceedings. Vol. 3. 2005. p. 1723-1726. 1610291 https://doi.org/10.1109/EUMC.2005.1610291