A 6-bit 1GS/s low-power flash ADC

Yu Chang Lien; Ying Zu Lin; Soon-Jyh Chang

doi:10.1109/VDAT.2009.5158132

A 6-bit 1GS/s low-power flash ADC

Yu Chang Lien, Ying Zu Lin, Soon-Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13μm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	211-214
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158132
Publication status	Published - 2009 Dec 1
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 2009 Apr 28 → 2009 Apr 30

Publication series

Name	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/Territory	Taiwan
City	Hsinchu
Period	09-04-28 → 09-04-30

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/VDAT.2009.5158132

Cite this

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title = "A 6-bit 1GS/s low-power flash ADC",

abstract = "This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13μm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.",

author = "Lien, {Yu Chang} and Lin, {Ying Zu} and Soon-Jyh Chang",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/VDAT.2009.5158132",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "211--214",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",

}

Lien, YC, Lin, YZ & Chang, S-J 2009, A 6-bit 1GS/s low-power flash ADC. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158132, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 211-214, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 09-04-28. https://doi.org/10.1109/VDAT.2009.5158132

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AU - Lin, Ying Zu

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PY - 2009/12/1

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N2 - This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13μm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.

AB - This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13μm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.

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M3 - Conference contribution

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BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Y2 - 28 April 2009 through 30 April 2009

ER -

A 6-bit 1GS/s low-power flash ADC

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