A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

Chun Cheng Liu, Yi Ting Huang, Guan Ying Huang, Soon Jyh Chang, Chung Ming Huang, Chih Haur Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages215-218
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 2009 Apr 282009 Apr 30

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Liu, C. C., Huang, Y. T., Huang, G. Y., Chang, S. J., Huang, C. M., & Huang, C. H. (2009). A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (pp. 215-218). [5158133] (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158133