A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process

Chun Cheng Liu, Yi Ting Huang, Guan Ying Huang, Soon-Jyh Chang, Chung-Ming Huang, Chih Haur Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages215-218
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 2009 Apr 282009 Apr 30

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period09-04-2809-04-30

Fingerprint

Digital to analog conversion
Capacitors
Electric power utilization
Sampling
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Liu, C. C., Huang, Y. T., Huang, G. Y., Chang, S-J., Huang, C-M., & Huang, C. H. (2009). A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 (pp. 215-218). [5158133] (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158133
Liu, Chun Cheng ; Huang, Yi Ting ; Huang, Guan Ying ; Chang, Soon-Jyh ; Huang, Chung-Ming ; Huang, Chih Haur. / A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. pp. 215-218 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).
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abstract = "This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81{\%}. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.",
author = "Liu, {Chun Cheng} and Huang, {Yi Ting} and Huang, {Guan Ying} and Soon-Jyh Chang and Chung-Ming Huang and Huang, {Chih Haur}",
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Liu, CC, Huang, YT, Huang, GY, Chang, S-J, Huang, C-M & Huang, CH 2009, A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158133, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 215-218, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 09-04-28. https://doi.org/10.1109/VDAT.2009.5158133

A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. / Liu, Chun Cheng; Huang, Yi Ting; Huang, Guan Ying; Chang, Soon-Jyh; Huang, Chung-Ming; Huang, Chih Haur.

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 215-218 5158133 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-μm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.

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Liu CC, Huang YT, Huang GY, Chang S-J, Huang C-M, Huang CH. A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-μm digital CMOS process. In 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 215-218. 5158133. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09). https://doi.org/10.1109/VDAT.2009.5158133