This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.