A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

Yu Po Cheng, Yen Long Lee, Ming Hung Chien, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
Publication statusPublished - 2016 May 31
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 2016 Apr 252016 Apr 27

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period16-04-2516-04-27

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

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