A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

Yu Po Cheng; Yen Long Lee; Ming Hung Chien; Soon Jyh Chang

doi:10.1109/VLSI-DAT.2016.7482531

A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

Yu Po Cheng, Yen Long Lee, Ming Hung Chien, Soon Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.

Original language	English
Title of host publication	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467394987
DOIs	https://doi.org/10.1109/VLSI-DAT.2016.7482531
Publication status	Published - 2016 May 31
Event	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan Duration: 2016 Apr 25 → 2016 Apr 27

Publication series

Name	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other	2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
Country/Territory	Taiwan
City	Hsinchu
Period	16-04-25 → 16-04-27

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation

Access to Document

10.1109/VLSI-DAT.2016.7482531

Cite this

Cheng, Y. P., Lee, Y. L., Chien, M. H., & Chang, S. J. (2016). A 7 Gb/s half-rate clock and data recovery circuit with compact control loop. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 Article 7482531 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482531

@inproceedings{660355a9dd974cd88e4b2f1c3f505556,

title = "A 7 Gb/s half-rate clock and data recovery circuit with compact control loop",

abstract = "This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.",

author = "Cheng, {Yu Po} and Lee, {Yen Long} and Chien, {Ming Hung} and Chang, {Soon Jyh}",

note = "Funding Information: The authors would like to thank the fabrication and measurement support of Chip Implementation Center (CIC), Taiwan. This work was supported in part by XXXXX Inc., and the Ministry of Science and Technology of Taiwan under Grant NSC-XXX-XXXX-E-XXX-XXX-XXX (keep blind). Publisher Copyright: {\textcopyright} 2016 IEEE. Copyright: Copyright 2016 Elsevier B.V., All rights reserved.; 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 ; Conference date: 25-04-2016 Through 27-04-2016",

year = "2016",

month = may,

day = "31",

doi = "10.1109/VLSI-DAT.2016.7482531",

language = "English",

series = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016",

address = "United States",

}

Cheng, YP, Lee, YL, Chien, MH & Chang, SJ 2016, A 7 Gb/s half-rate clock and data recovery circuit with compact control loop. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482531, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482531

A 7 Gb/s half-rate clock and data recovery circuit with compact control loop. / Cheng, Yu Po; Lee, Yen Long; Chien, Ming Hung et al.
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482531 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

AU - Cheng, Yu Po

AU - Lee, Yen Long

AU - Chien, Ming Hung

AU - Chang, Soon Jyh

N1 - Funding Information: The authors would like to thank the fabrication and measurement support of Chip Implementation Center (CIC), Taiwan. This work was supported in part by XXXXX Inc., and the Ministry of Science and Technology of Taiwan under Grant NSC-XXX-XXXX-E-XXX-XXX-XXX (keep blind). Publisher Copyright: © 2016 IEEE. Copyright: Copyright 2016 Elsevier B.V., All rights reserved.

PY - 2016/5/31

Y1 - 2016/5/31

N2 - This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.

AB - This paper presents a compact control loop and a digitalized stepwise control method to improve area and power efficiency for digital-based clock and data recovery circuits (CDRs). By combining the frequency control loop and integral path with a digital adder, some tributary circuits are removed to save total area and power. Meanwhile, the stepwise control technique for constant system bandwidth is digitalized to enhance the system robustness. The digital-based CDR is designed and fabricated in 90-nm GUTM CMOS process. The measured root mean square (rms) jitter ratio of the synchronous clock and recovered data are 3.2% (9.25 ps) and 0.048UI (13.66 ps) and the peak to peak jitter are 64.38 ps (22.5 %) and 65.63 ps (23 %) while the input data pattern is 7 Gb/s PRBS7. The core area of the test chip is 0.054 mm2 and its power efficiency is 1.623 mW/Gb/s.

UR - http://www.scopus.com/inward/record.url?scp=84978370270&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84978370270&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2016.7482531

DO - 10.1109/VLSI-DAT.2016.7482531

M3 - Conference contribution

AN - SCOPUS:84978370270

T3 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

BT - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Y2 - 25 April 2016 through 27 April 2016

ER -

Cheng YP, Lee YL, Chien MH, Chang SJ. A 7 Gb/s half-rate clock and data recovery circuit with compact control loop. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482531. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). doi: 10.1109/VLSI-DAT.2016.7482531

A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

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