A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch

Tsung Chih Hung, Tai Haur Kuo

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper proposes averaging correlated level shifting (ACLS) and reference swapping (RS) techniques for simultaneously reducing errors from the finite opamp gain and capacitor mismatch in a pipelined analog-to-digital converter (ADC). The ACLS technique reduces the sensitivity of ADC accuracy to the opamp gain by averaging the finite opamp gain errors in two amplifying phases, where the error in the second amplifying phase is designed to have the opposite polarity to the one in the first amplifying phase. Meanwhile, ACLS also decreases the opamp's thermal noise. In addition, the RS utilizes the averaging operation to reduce capacitor random mismatch error and combines a simple capacitor layout arrangement to decrease capacitor gradient mismatch error. Using the ACLS and RS techniques, a 16-bit ring amplifier-based pipelined ADC without calibration is realized in a 90-nm CMOS technology. Operating at 24 MS/s for a 10-MHz sine wave input, the proposed ADC achieves a 74.3-dB signal-to-noise-and-distortion ratio (SNDR) and 85.5-dB spurious free dynamic range (SFDR), and consumes 5.1 mW, yielding Walden and Schreier figure of merits of 50.1 fJ/conversion-step and 168 dB, respectively.

Original languageEnglish
Article number08645697
Pages (from-to)1425-1435
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number5
DOIs
Publication statusPublished - 2019 May

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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