A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ying Zu Lin, Chun Cheng Liu, Guan Ying Huang, Ya Ting Shyu, Soon-Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Citations (Scopus)

Abstract

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversionstep, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Circuits, VLSIC 2010
Pages243-244
Number of pages2
DOIs
Publication statusPublished - 2010 Oct 22
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States
Duration: 2010 Jun 162010 Jun 18

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
CountryUnited States
CityHonolulu, HI
Period10-06-1610-06-18

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lin, Y. Z., Liu, C. C., Huang, G. Y., Shyu, Y. T., & Chang, S-J. (2010). A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS. In 2010 Symposium on VLSI Circuits, VLSIC 2010 (pp. 243-244). [5560246] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2010.5560246