A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ying Zu Lin; Chun Cheng Liu; Guan Ying Huang; Ya Ting Shyu; Soon-Jyh Chang

doi:10.1109/VLSIC.2010.5560246

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

Ying Zu Lin, Chun Cheng Liu, Guan Ying Huang, Ya Ting Shyu, Soon-Jyh Chang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

49 Citations (Scopus)

Abstract

This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversionstep, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

Original language	English
Title of host publication	2010 Symposium on VLSI Circuits, VLSIC 2010
Pages	243-244
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2010.5560246
Publication status	Published - 2010 Oct 22
Event	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI, United States Duration: 2010 Jun 16 → 2010 Jun 18

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2010 24th Symposium on VLSI Circuits, VLSIC 2010
Country/Territory	United States
City	Honolulu, HI
Period	10-06-16 → 10-06-18

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/VLSIC.2010.5560246

Cite this

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title = "A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS",

abstract = "This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversionstep, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.",

author = "Lin, {Ying Zu} and Liu, {Chun Cheng} and Huang, {Guan Ying} and Shyu, {Ya Ting} and Soon-Jyh Chang",

year = "2010",

month = oct,

day = "22",

doi = "10.1109/VLSIC.2010.5560246",

language = "English",

isbn = "9781424476367",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "243--244",

booktitle = "2010 Symposium on VLSI Circuits, VLSIC 2010",

note = "2010 24th Symposium on VLSI Circuits, VLSIC 2010 ; Conference date: 16-06-2010 Through 18-06-2010",

}

Lin, YZ, Liu, CC, Huang, GY, Shyu, YT & Chang, S-J 2010, A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS. in 2010 Symposium on VLSI Circuits, VLSIC 2010., 5560246, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 243-244, 2010 24th Symposium on VLSI Circuits, VLSIC 2010, Honolulu, HI, United States, 10-06-16. https://doi.org/10.1109/VLSIC.2010.5560246

TY - GEN

T1 - A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

AU - Lin, Ying Zu

AU - Liu, Chun Cheng

AU - Huang, Guan Ying

AU - Shyu, Ya Ting

AU - Chang, Soon-Jyh

PY - 2010/10/22

Y1 - 2010/10/22

N2 - This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversionstep, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

AB - This paper reports a subranged SAR ADC consisting of a 3.5-bit flash coarse ADC, a 6-bit SAR fine ADC, and a differential segmented capacitive DAC. The flash ADC controls thermometer MSBs of the DAC and SAR ADC controls the binary LSBs. The segmented DAC improves DNL during MSB transitions. The merged switching of MSB capacitors enhances operation speed. The 9-bit 150-MS/s ADC consumes 1.53 mW from a 1.2-V supply. The ENOB is 8.69 bit and ERBW is 100 MHz. The FOMs at 1.2 V, 150 MS/s and 1 V, 100 MS/s are 24.7 and 17.7 fJ/conversionstep, respectively. At 1.3-V supply voltage, the sampling rate achieves 200 MS/s.

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BT - 2010 Symposium on VLSI Circuits, VLSIC 2010

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ER -

A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS

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