A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

Kai Cheng Cheng; Soon Jyh Chang; Chung Chieh Chen; Shuo Hong Hung

doi:10.1109/LSSC.2025.3544649

A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

Kai Cheng Cheng
, Soon Jyh Chang
, Chung Chieh Chen
, Shuo Hong Hung

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes 107.38μ W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.

Original language	English
Pages (from-to)	65-68
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	8
DOIs	https://doi.org/10.1109/LSSC.2025.3544649
Publication status	Published - 2025

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/LSSC.2025.3544649

Cite this

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title = "A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator",

abstract = "This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes 107.38μ W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.",

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AU - Chen, Chung Chieh

AU - Hung, Shuo Hong

PY - 2025

Y1 - 2025

N2 - This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes 107.38μ W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.

AB - This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC can achieve sharp NTF with only two dynamic amplifiers and is insensitive to process, voltage, and temperature (PVT) variation. The NS-SAR ADC occupies 0.09 mm2 in a 28-nm CMOS process. With a 1-V supply voltage, it consumes 107.38μ W at 5 MS/s. The measured signal-to-noise and distortion ratio (SNDR) is 94.3 dB over a 100-kHz bandwidth (BW), resulting in a Schreier figure of merit (FoM) of 184 dB and a Walden FoM of 12.6 fJ/conv.-step.

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A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

Abstract

All Science Journal Classification (ASJC) codes

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