TY - GEN
T1 - A 9.8-fJ/conv.-step FoMW8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators
AU - Wang, Jia Ching
AU - Li, Bing Yang
AU - Kuo, Tai Haur
N1 - Funding Information:
The authors would like to acknowledge the chip fabrication provided by Taiwan Semiconductor Research Institute (TSRI), Taiwan.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents an 8b 2.5-GS/s single-channel CDAC-assisted three-stage subranging ADC using reference-embedded comparators (RECs). In this work, both the power consumption and calibration overhead of the RECs are largely reduced by a simple capacitor DAC (CDAC) designed for this subranging ADC. In addition, the severe CDAC gain error is also largely reduced by a simple gain error compensation design, which is not only insensitive to the PVT variation but is also a low-complexity design. This ADC is implemented in 28-nm CMOS technology and occupies an active area of 0.024 mm2. With a Nyquist-rate input at 2.5 GS/s, the measured SNDR is 44.8 dB with a 3.5-mW power consumption only. This ADC achieves a Walden Figure-of-Merits of 9.8 fJ/conv.-step only. Compared to the single-channel prior-art ADCs with a sampling rate =1.5 GS/s and a resolution of 6-10b, this work advances the state-of-the-art by nearly 2×.
AB - This paper presents an 8b 2.5-GS/s single-channel CDAC-assisted three-stage subranging ADC using reference-embedded comparators (RECs). In this work, both the power consumption and calibration overhead of the RECs are largely reduced by a simple capacitor DAC (CDAC) designed for this subranging ADC. In addition, the severe CDAC gain error is also largely reduced by a simple gain error compensation design, which is not only insensitive to the PVT variation but is also a low-complexity design. This ADC is implemented in 28-nm CMOS technology and occupies an active area of 0.024 mm2. With a Nyquist-rate input at 2.5 GS/s, the measured SNDR is 44.8 dB with a 3.5-mW power consumption only. This ADC achieves a Walden Figure-of-Merits of 9.8 fJ/conv.-step only. Compared to the single-channel prior-art ADCs with a sampling rate =1.5 GS/s and a resolution of 6-10b, this work advances the state-of-the-art by nearly 2×.
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U2 - 10.1109/VLSITechnologyandCir46769.2022.9830239
DO - 10.1109/VLSITechnologyandCir46769.2022.9830239
M3 - Conference contribution
AN - SCOPUS:85135248944
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 92
EP - 93
BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Y2 - 12 June 2022 through 17 June 2022
ER -