A bias-driven approach for automated design of operational amplifiers

Cheng Wu Lin, Pin Dai Sue, Ya Ting Shyu, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables into transistor dimensions without much preparing effort. The layout generation employs analog layout skills, such as device matching, dummy cell and guard ring, to have good quality.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages118-121
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 2009 Apr 282009 Apr 30

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Other

Other2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/TerritoryTaiwan
CityHsinchu
Period09-04-2809-04-30

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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