TY - GEN
T1 - A bias-driven approach for automated design of operational amplifiers
AU - Lin, Cheng Wu
AU - Sue, Pin Dai
AU - Shyu, Ya Ting
AU - Chang, Soon Jyh
PY - 2009/12/1
Y1 - 2009/12/1
N2 - This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables into transistor dimensions without much preparing effort. The layout generation employs analog layout skills, such as device matching, dummy cell and guard ring, to have good quality.
AB - This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables into transistor dimensions without much preparing effort. The layout generation employs analog layout skills, such as device matching, dummy cell and guard ring, to have good quality.
UR - http://www.scopus.com/inward/record.url?scp=77950677150&partnerID=8YFLogxK
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U2 - 10.1109/VDAT.2009.5158109
DO - 10.1109/VDAT.2009.5158109
M3 - Conference contribution
AN - SCOPUS:77950677150
SN - 9781424427826
T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
SP - 118
EP - 121
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Y2 - 28 April 2009 through 30 April 2009
ER -