A BIST scheme for FPGA interconnect delay faults

Chun Chieh Wang, Jing Jia Liou, Yen Lin Peng, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

In this paper, we propose a new BIST-based approach for testing FPGA interconnect delay faults. The BIST architecture utilizes the regularity of an FPGA by implementing small test circuits repetitively over FPGA's CLB arrays. Each test circuit targets a specific path and determine conformance of the path delay according to a test clock. With the target path configured as a loop back in the test circuit, test accuracy of the path delay can be increased with reduced effects from skews of the test clocks. Thus, this BIST has a higher delay fault coverage, since it is not necessary to apply guard bands for skews in test mode.

Original languageEnglish
Title of host publicationProceedings - 23rd IEEE VLSI Test Symposium, VTS 2005
Pages201-206
Number of pages6
DOIs
Publication statusPublished - 2005 Dec 1
Event23rd IEEE VLSI Test Symposium, VTS 2005 - Palm Springs, CA, United States
Duration: 2005 May 12005 May 5

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference23rd IEEE VLSI Test Symposium, VTS 2005
CountryUnited States
CityPalm Springs, CA
Period05-05-0105-05-05

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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  • Cite this

    Wang, C. C., Liou, J. J., Peng, Y. L., Huang, C. T., & Wu, C. W. (2005). A BIST scheme for FPGA interconnect delay faults. In Proceedings - 23rd IEEE VLSI Test Symposium, VTS 2005 (pp. 201-206). [1443423] (Proceedings of the IEEE VLSI Test Symposium). https://doi.org/10.1109/VTS.2005.5